3D Junctionless Ferroelectric NOR Memory With Air-Gap Isolation
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Solution Overview
Problem
Current memory structures face challenges in achieving high-density, low read-latency, and low-cost memory arrays with fast erase/write endurance, particularly in three-dimensional configurations, due to limitations in ferroelectric transistor endurance and integration with logic circuits.
Innovation Solution
The development of three-dimensional NOR memory strings using junctionless ferroelectric storage transistors with a ferroelectric gate dielectric layer, where each transistor shares a common source and drain line, and is isolated by a semiconductor oxide layer, allowing for individual addressing and low-voltage operation, and the use of air gaps for reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional arrays of thin-film storage transistors are used to achieve high-density memory, then memory density is improved, but read latency and write endurance deteriorate due to limitations in ferroelectric transistor performance and integration complexity
Solution Approach 1:
The patent transitions from planar two-dimensional memory arrays to three-dimensional vertically stacked memory structures. Multiple layers of memory strings are stacked above a substrate, with bit lines extending vertically through the stack to access storage nodes at different heights. This vertical stacking enables high-density memory organization while maintaining short access paths through the use of through-silicon via connections and vertical bit line routing.
2Quantity of substance
If three-dimensional arrays of thin-film storage transistors are used to achieve high-density memory, then memory density is improved, but write endurance deteriorates due to limitations in ferroelectric transistor performance
Solution Approach 1:
The patent employs specific material parameter optimization to enhance write endurance. A tunnel dielectric layer with thickness of 5-15 nm provides reliable charge trapping, while a blocking layer with thickness of 10-30 nm prevents charge leakage. The ferroelectric gate dielectric layer uses specific compositions (such as hafnium oxide with aluminum doping) and thickness ranges (5-20 nm) to achieve stable polarization states that can withstand repeated write cycles. These parameter optimizations enable the three-dimensional structure to maintain high write endurance despite the increased stress from vertical stacking.
3Ease of manufacture
If conventional ferroelectric transistors are used in three-dimensional arrays, then fabrication is simplified, but manufacturing precision deteriorates due to challenges in forming vertical structures and isolating memory strings
Solution Approach 1:
The patent segments the three-dimensional memory structure into distinct functional layers that can be fabricated separately and then integrated. The structure is divided into: (1) substrate layer with access transistors, (2) tunnel dielectric layer with charge trapping region, (3) blocking layer, (4) ferroelectric gate dielectric layer, (5) gate electrode layer, and (6) vertical bit line structures. Each layer is formed using specialized deposition and etching processes, allowing precise control over vertical dimensions and interfaces while maintaining overall fabrication feasibility.
4Quantity of substance
If memory strings are closely packed to increase density, then memory density is improved, but parasitic capacitance increases due to reduced spacing between adjacent strings
Solution Approach 1:
The patent introduces air gaps as intermediary spaces between adjacent vertical memory strings and between the memory stack and surrounding structures. These air gaps, formed by selective removal of sacrificial materials or by direct deposition techniques, provide electrical isolation that reduces parasitic capacitance coupling between neighboring bit lines and storage nodes. The air gap geometry allows closely packed memory strings to maintain low inter-string capacitance, enabling high-density integration without significant energy loss from parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density, low-cost memory arrays with improved endurance, low read latency, and scalability, facilitating integration with logic circuits while reducing physical space and thermal damage, and enhancing switching performance and data retention.
Implementation Method 1
a ferroelectric gate dielectric layer, where each transistor shares a common source and drain line
Implementation Method 2
the use of air gaps for reduced parasitic capacitance
Data Source
AI summary
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The ferroelectric storage transistors are junctionless field-effect transistors having a ferroelectric polarization layer formed adjacent a semiconductor oxide layer as the channel region. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process.