Junctionless Transistor Channel Segmentation for NAND Flash
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Solution Overview
Problem
Flash memory devices face issues with inadvertent programming or disturbances of unselected cells during program operations, leading to data integrity concerns and program disturbances, especially in NAND flash memory systems.
Innovation Solution
The implementation of junctionless transistors with fringe-field induced (virtual) source and drains, and a method to suppress the formation of inversion-layer sources and drains, creating a discontinuous channel in program inhibit strings to prevent unintended programming and disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional flash memory cells are used during program operation, then programming speed and density are achieved, but inadvertent programming and disturbances of unselected cells occur
Solution Approach 1:
The patent segments the channel into continuous and discontinuous regions by controlling inversion layer formation. Selected strings maintain continuous channels for programming, while program inhibit strings have discontinuous channels that prevent inadvertent programming of unselected cells. This segmentation allows simultaneous high-speed programming and data protection.
Solution Approach 2:
The patent applies different electrical characteristics to different regions: selected strings receive voltages that form inversion layers for continuous channels, while program inhibit strings receive suppressed voltages that prevent inversion layer formation. This local differentiation enables targeted programming without disturbing unselected cells.
2Reliability
If program inhibit voltages are applied to unselected strings, then data protection is improved, but channel continuity is disrupted and programming efficiency decreases
Solution Approach 1:
The channel is segmented into continuous regions in selected strings and discontinuous regions in program inhibit strings. This segmentation allows program inhibit voltages to be applied without affecting the continuity of channels in selected strings, thus maintaining programming efficiency while protecting unselected cells.
Solution Approach 2:
The patent changes the electrical parameters (voltage levels) applied to different string types dynamically during operation. Selected strings receive high voltages for inversion layer formation, while program inhibit strings receive suppressed voltages. This parameter differentiation enables simultaneous data protection and efficient programming.
3Productivity
If inversion layers are formed in all strings during programming, then programming speed is maintained, but unselected cells experience program disturbance
Solution Approach 1:
The patent creates local differences in inversion layer formation: selected strings have inversion layers formed for fast programming, while program inhibit strings have inversion layer formation suppressed. This local quality control prevents program disturbance in unselected cells while maintaining high programming speed in selected strings.
Solution Approach 2:
The patent dynamically changes voltage parameters during programming operations. Selected strings are subjected to high voltage pulses that form inversion layers rapidly, while program inhibit strings are kept at suppressed voltage levels. This parameter control eliminates program disturbance without sacrificing programming speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively inhibits inadvertent programming of unselected cells and reduces program disturbances, enhancing data protection and integrity by maintaining a discontinuous channel in program inhibit strings, even when cells have already been programmed.
Implementation Method 1
cell transistors contain fringe field induced (virtual) source and drains
Implementation Method 2
suppressing the formation of an inversion-layer source and drain in at least one of the junctionless transistors
Data Source
AI summary
A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include NAND flash memory cells composed of junctionless transistors, and has a set of wordlines. During program operation, a selected wordline of the set of wordlines is biased at a program voltage, and wordline voltage low enough to suppress the formation of source/drains is applied on at least one word line on a source side of the selected wordline such that a channel isolation occurs thereby causing the discontinuous channel in the at least string.


