Junctionless Transistor Latch for Non-Volatile Memory Data Retention
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices face challenges in reducing chip area while maintaining high memory capacity and preventing data loss during power shutdown, as they rely on volatile inverter latches or require additional non-volatile memory for data retention.
Innovation Solution
A non-volatile semiconductor memory device with a latch configuration using junctionless field-effect transistors and a capacitor, integrated into a stair-like step portion, which reduces chip area and ensures data retention without the need for additional non-volatile memory, utilizing oxide semiconductor layers for low off-leak current and long retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile inverter latch is used for data buffering, then programming speed is improved, but data loss occurs during power shutdown
Solution Approach 1:
The patent changes the operational state of the latch by introducing a control signal that switches between volatile mode (for fast programming) and non-volatile mode (for data retention). The junctionless transistor's conductivity type is dynamically changed to maintain data in the capacitor during power shutdown, resolving the contradiction between speed and reliability.
2Reliability
If additional non-volatile memory is added for data retention, then data loss is prevented, but chip area increases
Solution Approach 1:
The patent merges the functions of volatile latch (for fast access) and non-volatile memory (for data retention) into a single integrated structure. The junctionless transistor with capacitor combination performs both temporary buffering and permanent data retention functions, eliminating the need for separate memory blocks and reducing chip area.
Solution Approach 2:
The latch circuit is designed to perform multiple functions: it acts as a volatile buffer during normal operation and transforms into a non-volatile storage element during power shutdown. The junctionless transistor's ability to maintain data in its depletion state provides universal functionality across different operational modes without requiring additional dedicated structures.
3Ease of manufacture
If conventional transistors are used in the latch, then manufacturing is simpler, but off-leak current is high and retention time is short
Solution Approach 1:
The patent employs a composite material structure where the junctionless transistor is formed with specific semiconductor layers (such as silicon-germanium or III-V族化合物半导体) that provide both low off-leak current and long retention time. The combination of these materials with the capacitor creates a structure that maintains data for extended periods while remaining compatible with existing manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses data loss during power shutdown and reduces chip area, enhancing memory capacity and operational efficiency by using a latch with junctionless field-effect transistors and a capacitor, maintaining high conductivity and simplifying the manufacturing process.
Implementation Method 1
a first oxide semiconductor layer
Data Source
AI summary
According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.