Junction-less Transistor Fabrication via Sandwich Doping and Wrap-Around Gate
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Solution Overview
Problem
Junction-less transistors face challenges with high channel resistance due to the continuous shrinkage of semiconductor devices, affecting their performance, and the difficulty in controlling doping processes for source, drain, and channel regions in field-effect transistors (FETs) leads to increased leakage currents and short-channel effects.
Innovation Solution
A method for fabricating junction-less transistors involves forming a semiconductor substrate with a dielectric layer and a semiconductor layer having a sandwich doping profile, including a first heavily doped layer, a lightly doped layer, and a second heavily doped layer, with trenches etched to form a chamber and a gate structure around the semiconductor layer, reducing channel resistance by forming a dual-gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the critical dimension of semiconductor devices is continuously shrunk, then the device size is reduced and integration density is improved, but threshold voltage drifting and leakage current increase
Solution Approach 1:
The patent changes the fundamental parameter of doping structure from conventional PN junctions to junction-less uniform doping. This parameter change eliminates the abrupt doping interfaces that cause threshold voltage drifting and leakage current, allowing devices to maintain stable electrical characteristics even at critically small dimensions
Solution Approach 2:
The patent extracts and removes the PN junction structure from the device design. By eliminating the junction regions between source/drain and channel, the patent removes the root cause of threshold voltage instability and leakage current, enabling reliable operation at scaled dimensions
2Volume of moving object
If the area of source region, drain region and channel region is reduced, then device size is shrunk, but doping process control becomes more difficult
Solution Approach 1:
The patent changes the doping parameter distribution from non-uniform (conventional FETs with different doping types and concentrations in source, drain, and channel) to uniform (junction-less transistor with same doping type and concentration throughout). This simplifies the doping process and reduces manufacturing precision requirements while maintaining device functionality
Solution Approach 2:
The patent applies homogeneity by using the same doping type and concentration for the source region, drain region, and channel region. This uniform doping approach eliminates the complexity of controlling multiple doping processes and reduces manufacturing precision requirements, as demonstrated by the consistent electrical characteristics achieved in the device
3Reliability
If junction-less transistor structure is adopted, then short-channel effect is prevented, but channel resistance becomes relatively large
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional wrap-around gate structure that envelops the channel from multiple dimensions. This multi-dimensional gating provides superior electrostatic control and enables effective short-channel effect suppression while maintaining reasonable channel resistance through enhanced field effect
Solution Approach 2:
The gate structure is nested around the channel region in a wrap-around configuration, with the gate wrapping partially or fully around the channel. This nested geometry provides enhanced control over the channel potential and enables effective short-channel effect suppression while managing channel resistance through improved electrostatics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces on-resistance and improves the performance of junction-less transistors by maintaining a doping concentration gradient and increasing the contact area between the semiconductor layer and the gate structure, enhancing their functionality.
Implementation Method 1
forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer
Data Source
AI summary
A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer. The method also includes etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and a portion of the dielectric layer; and removing the portion of the dielectric layer between the adjacent trenches to form a chamber. Further, the method includes forming a gate structure around the portion of the semiconductor layer between the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure.