Junctionless Transistor Parasitic Capacitance Reduction
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Solution Overview
Problem
Junctionless transistors face challenges with high source-drain parasitic capacitance and low thermal stability, affecting their performance, especially as device sizes shrink and manufacturing costs increase with silicon-on-insulator substrates.
Innovation Solution
A method for forming junctionless transistors and complementary junctionless transistors involves creating a semiconductor substrate with a first-type doped well, an isolation layer, and an active layer with a dielectric layer to reduce parasitic capacitance and enhance thermal stability by suspending active layer portions and forming gate structures with specific doping types, thereby reducing capacitance and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a junctionless transistor uses a homogeneous material substrate, then the device structure is simple and manufacturing is easier, but the source-drain parasitic capacitance increases which seriously affects transistor performance
Solution Approach 1:
The substrate is segmented into different material regions: a first substrate region with high thermal conductivity material and a second substrate region with low thermal conductivity material. This segmentation allows the device to simultaneously achieve good heat dissipation performance and high parasitic capacitance, resolving the contradiction between ease of manufacture and transistor performance
Solution Approach 2:
Different regions of the substrate are assigned different material properties: the first substrate region under the channel uses high thermal conductivity material for heat dissipation, while the second substrate region uses low thermal conductivity material to reduce parasitic capacitance. This local differentiation resolves the contradiction by optimizing each region for its specific function
2Reliability
If a junctionless transistor uses a silicon-on-insulator substrate, then the parasitic capacitance between source/drain and substrate is reduced, but the manufacturing cost increases significantly for small critical dimensions
Solution Approach 1:
An isolation layer is introduced as an intermediary between the active layer and the substrate. This isolation layer with appropriate dielectric properties reduces parasitic capacitance between the source/drain and substrate while being compatible with standard manufacturing processes, thus resolving the contradiction between parasitic capacitance reduction and manufacturing cost
3Reliability
If a junctionless transistor uses a silicon-on-insulator substrate, then parasitic capacitance is reduced, but the thermal conductivity of buried layers decreases causing heat generation in the channel region
Solution Approach 1:
The substrate is segmented into different material regions: a first substrate region with high thermal conductivity material and a second substrate region with low thermal conductivity material. This segmentation allows the device to simultaneously achieve good heat dissipation performance and high parasitic capacitance, resolving the contradiction between ease of manufacture and transistor performance
Solution Approach 2:
Different regions of the substrate are assigned different material properties: the first substrate region under the channel uses high thermal conductivity material for heat dissipation, while the second substrate region uses low thermal conductivity material to reduce parasitic capacitance. This local differentiation resolves the contradiction by optimizing each region for its specific function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and enhances thermal stability, improving the performance of junctionless transistors and complementary junctionless transistors by isolating the source and drain from the substrate and allowing better heat management.
Implementation Method 1
A junctionless transistor having a homogeneous material as substrate may have high source-drain parasitic capacitance in regions surrounding source and drain, which can seriously affect performance of the junctionless transistor
Implementation Method 2
a first-type doped well is formed in the semiconductor substrate. An isolation layer doped with a first-type ion is formed on the semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer
Implementation Method 3
A gate structure is formed on the first portion of the active layer
Data Source
AI summary
Fabrication methods for junctionless transistor and complementary junctionless transistor. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer.