K-bit prefetch section for memory device data I/O speed
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Solution Overview
Problem
Conventional memory devices face limitations in increasing data I/O speed beyond a certain level due to physical constraints on access clock speed, making it difficult to enhance data transfer rates using existing DRAM fabrication technologies.
Innovation Solution
A memory device configuration that includes a memory cell array, a row decoding section, a K-bit prefetch section, and an output buffer, where the K-bit prefetch section decodes a column address to prefetch K data from memory cells connected to an activated word line, using a second clock frequency that is 1/M of the first clock frequency, with M being a real number other than a power of 2, allowing for increased data I/O speed without exceeding physical clock limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data I/O speed is increased by using conventional DRAM fabrication technologies, then the data transfer rate is improved, but the access clock speed reaches physical limits that cannot be exceeded
Solution Approach 1:
The patent implements a prefetch mechanism that pre-loads data into a buffer before the buffer is fully consumed. The K-bit prefetch section decodes column addresses and fetches K data from memory cells in advance, allowing the output buffer to operate at higher speeds without requiring the memory array access clock to be proportionally faster. This preliminary data retrieval action decouples the output data rate from the array access rate.
Solution Approach 2:
The patent introduces an intermediate buffer structure between the memory array and the output interface. The output buffer acts as a mediator that receives data from the memory array at one rate (determined by access clock) and outputs data at a different, higher rate (determined by data I/O clock). This intermediary buffer allows the system to achieve fast data I/O speeds without being constrained by the physical limits of the memory array access speed.
2Productivity
If the access clock frequency is increased to improve data transfer rate, then the data I/O speed increases, but the physical constraints of DRAM fabrication technologies are exceeded
Solution Approach 1:
The prefetch mechanism performs preliminary data retrieval operations at manageable clock frequencies. By pre-decoding column addresses and pre-fetching K data items into the output buffer, the system prepares data in advance without requiring the memory array to operate at excessively high frequencies. This allows the memory array to operate within fabrication constraints while the output interface achieves high transfer rates.
Solution Approach 2:
The patent changes the operational parameters by introducing a prefetch depth parameter K and a buffer depth parameter. These parameters allow the system to adjust the balance between memory array access rate and output data rate independently. The K-bit prefetch section can be configured to fetch different amounts of data, and the output buffer can be sized to hold varying amounts of data, allowing optimization within fabrication constraints.
3Ease of manufacture
If conventional DRAM architecture is used, then manufacturing is straightforward, but data I/O speed cannot be sufficiently increased
Solution Approach 1:
The patent adds a preliminary prefetch action to the conventional DRAM architecture. The K-bit prefetch section operates in advance to load data into the output buffer before the buffer needs to be read out. This preliminary action enables the output interface to operate at high speeds without requiring fundamental changes to the core memory array architecture, thus maintaining ease of manufacture while achieving high data I/O speeds.
Solution Approach 2:
The output buffer serves as an intermediary component that bridges the conventional memory array and the high-speed output interface. This intermediary allows the system to retain the simple, well-understood conventional DRAM array architecture while achieving high data transfer rates through the buffer's ability to decouple the access rate from the output rate.
Data Source
AI summary
A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.