KASUMI Ciphering Parallelization for Cycle Reduction
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Solution Overview
Problem
The KASUMI ciphering process in hardware implementations is slow, requiring multiple modules to maintain data processing speed, which increases physical area, power consumption, and costs, necessitating an improvement in processing speed.
Innovation Solution
The KASUMI ciphering process is optimized by unrolling the eight rounds and computing two consecutive FI functions and FL functions in parallel, reducing the total number of cycles from 32 to 17, allowing for faster data processing without increasing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple KASUMI modules are used to improve processing speed, then the data processing speed is maintained, but the physical area, power consumption, and costs increase
Solution Approach 1:
The patent applies dynamics by making the KASUMI computation process adjustable and reconfigurable. The system can dynamically switch between different operation modes (normal operation vs. power-saving mode) and adjust the number of parallel KASUMI modules active based on traffic conditions. This allows the processing speed to be maintained when needed while reducing resource consumption during low-traffic periods, effectively resolving the contradiction between speed and physical area/power consumption.
Solution Approach 2:
The patent changes the operational parameters of the KASUMI modules by introducing a power-saving mode that reduces the computation frequency from the standard 32 cycles per output to 17 cycles per output. This parameter change allows the system to maintain adequate processing speed while significantly reducing the number of modules required, thereby decreasing physical area and power consumption without completely sacrificing performance.
2Speed
If multiple KASUMI modules are used to improve processing speed, then the data processing speed is maintained, but the power consumption increases
Solution Approach 1:
The system dynamically adjusts power consumption by switching between different operational modes. During high-traffic periods, multiple KASUMI modules operate at full speed (32 cycles per output) to maintain processing throughput. During low-traffic periods, the system transitions to power-saving mode with fewer modules operating at reduced computation frequency (17 cycles per output), significantly reducing power consumption while maintaining adequate processing capability.
Solution Approach 2:
The patent implements periodic assessment of traffic conditions to determine the appropriate operational mode. The system periodically evaluates whether normal speed mode or power-saving mode should be active, allowing it to adapt its power consumption patterns to match actual processing demands, thereby reducing unnecessary energy usage during low-traffic intervals.
3Device complexity
If software simulation is used to implement KASUMI, then hardware complexity is reduced, but processing speed decreases
Solution Approach 1:
The patent resolves this contradiction by making the implementation approach dynamic rather than static. The system can switch between software-based KASUMI computation and hardware-accelerated computation based on performance requirements. This allows the system to use software simulation when hardware resources are constrained or when lower speeds are acceptable, and to engage hardware modules when high processing speed is critical, thus balancing complexity and speed requirements.
Data Source
AI summary
An arrangement is provided for performing the KASUMI ciphering process. The arrangement includes apparatuses and methods that parallelize computations of two FI functions in KASUMI rounds within one clock cycle and computes two consecutive FL functions in the KASUMI rounds within one clock cycle.