Kautz NoC Processor with Addressing Strings for Visual Recognition
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Solution Overview
Problem
Neocortical computing processors face challenges in performing brain-mimicking visual recognition tasks due to the need for extensive matrix operations and high inter-stage data bandwidth, requiring several hundred Giga operations per second and over 1.5 Tera bits per second data transfer.
Innovation Solution
A network on chip processor with multiple cores and a Kautz NoC architecture, where each core has an addressing string with specific properties and is unidirectionally linked to other cores, utilizing a routing method that minimizes hop count and avoids congestion and faults, enabling efficient packet transmission and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional processors are used for visual recognition tasks, then the architecture is simple, but the computing performance and inter-stage data bandwidth are insufficient
Solution Approach 1:
The processor is divided into multiple independent cores (first core, second core, third core, fourth core) that can perform matrix operations in parallel. Each core has its own addressing string and connects through a Kautz NoC, enabling distributed computation that achieves high GOPS while maintaining manageable complexity through modular design
Solution Approach 2:
The patent introduces a multi-dimensional addressing string structure with L based-D words where each word has D possible values. This creates a D^L dimensional addressing space that enables efficient routing and data distribution across the heterogeneous multi-core architecture, achieving high bandwidth without proportional complexity increase
2Productivity
If more cores are added to increase computing power, then the matrix operation capability improves, but the inter-stage communication bandwidth requirement increases
Solution Approach 1:
Multiple cores are merged into a unified heterogeneous architecture where different cores can have different addressing strings. The Kautz NoC merges the communication paths of all cores into an integrated network that efficiently distributes data and collects results, achieving high aggregate bandwidth through coordinated communication
Solution Approach 2:
The addressing strings are pre-configured with specific patterns where neighboring words follow deterministic rules. This preliminary arrangement of addressing strings enables predictable routing paths that optimize data flow before computation begins, reducing communication overhead during matrix operations
3Reliability
If a complex routing method is used to avoid congestion and faults, then the reliability improves, but the routing complexity increases
Solution Approach 1:
The routing method incorporates feedback mechanisms where the Kautz NoC monitors packet transmission status and adjusts routing decisions based on congestion and fault conditions. The routing string generation process uses feedback from the network state to select optimal paths, improving reliability without requiring overly complex routing algorithms
Solution Approach 2:
The routing method dynamically changes routing parameters based on network conditions. By adjusting the routing string and hop count based on real-time congestion and fault information, the system achieves high reliability through adaptive routing rather than complex static routing algorithms
Data Source
AI summary
An exemplary embodiment of the present disclosure illustrates a network on chip processor including multiple cores and a Kautz NoC. Each of the cores is assigned with an addressing string with L based-D words, and the addressing string does not have two neighboring identical words, wherein L present of an addressing string length is an integer larger than 1, D present of a word selection is an integer larger than 2. Each of the cores is unidirectionally link to other (D−1) cores through the Kautz NoC, and in the two connected cores, the last (L−1) words associated with the addressing string of one core are same as the first (L−1) words associated with the addressing string of the other core.