Keccak Round Instruction Atomic Execution

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Solution Overview

Problem

Current secure communications protocols, such as TLS and IPsec, face significant overhead and latency issues when upgrading to post-quantum cryptography, particularly due to the compute-intensive nature of SHA3/Keccak functions, which are exacerbated by large state sizes and limitations in traditional instruction sets, leading to reduced connection rates and inefficiencies in embedded cores.

Innovation Solution

The implementation of improved Keccak hardware execution using a single instruction to perform 24 rounds atomically, with 1600-bit input and output, and leveraging processor registers to store the state, reducing the need for dedicated memory and minimizing latency by integrating multiple rounds per cycle, and utilizing existing load/store instructions for efficient data handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SHA3 permutation is implemented using traditional instruction sets with bit-shifts, bit-rotations and Boolean operations on 1600-bit state variable, then cryptographic hash functionality is achieved, but execution speed becomes slower and processing efficiency deteriorates

Engineering Contradiction:
ImproveSHA3 execution speedVSAvoidprocessing efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent divides the 1600-bit state variable into 32 separate 64-bit registers (R0-R31), allowing parallel processing of different segments of the state. This segmentation enables multiple bit operations to be performed simultaneously on different segments, dramatically improving execution speed and processing efficiency compared to traditional sequential processing of the entire 1600-bit state.

Inventive Principle:
Principle #1Segmentation

2Reliability

If SHA3 supports large input block size of 1088-bit with 24 rounds, then security guarantee is improved, but software implementation becomes slower

Engineering Contradiction:
Improvesecurity guaranteeVSAvoidsoftware implementation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent combines multiple rounds of Keccak processing into a single fused instruction that performs all 24 rounds atomically. By merging the 24 separate round operations into one unified hardware-accelerated instruction, the patent maintains the full security guarantee of 24 rounds while dramatically improving execution speed through parallel processing and atomic execution, eliminating the overhead of multiple separate software function calls.

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If processor registers are used to store the 1600-bit state instead of dedicated memory, then access speed is improved, but register resource consumption increases

Engineering Contradiction:
Improvestate access speedVSAvoidregister resource usage
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent utilizes existing general-purpose 64-bit registers (R0-R31) for cryptographic state storage, making these registers serve dual purposes: both traditional general-purpose computing tasks and SHA3/Keccak cryptographic operations. This multi-functionality approach allows the processor to maintain high state access speed using familiar register resources without requiring dedicated cryptographic registers, thereby avoiding increased device complexity while achieving fast cryptographic processing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Loss of time

If a single instruction performs 24 rounds atomically with 1600-bit input and output, then latency is reduced, but instruction complexity increases

Engineering Contradiction:
Improveprocessing latencyVSAvoidinstruction complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/software-based sequential execution of 24 separate round operations with a single hardware-accelerated atomic instruction. This substitution uses dedicated cryptographic execution units and datapaths within the processor to perform all 24 rounds in one atomic hardware operation, dramatically reducing processing latency from multiple sequential software instructions to a single hardware instruction execution.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP4488828A1Keccak round instruction and support
Publication Date: 2025.01.08 INTEL CORP
  • EP4488828A1 patent drawingFigure 1
  • EP4488828A1 patent drawingFigure 2
  • EP4488828A1 patent drawingFigure 3

AI summary

Techniques for Keccak permutation are described. In some examples, Keccak permutation is in response to a single instruction that includes one or more fields for source addressing information wherein the addressed source is to store an input 1600-bit state, one or more fields for destination addressing information that is to store an output 1600-bit state, a field for an identifier of a destination operand, and a field for an opcode, the opcode to indicate execution circuitry is to do perform an atomic Keccak permutation.