Keephot Instructions for Power Delivery Network Stability

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Solution Overview

Problem

Conventional hardware emulators experience significant voltage fluctuations during load steps, leading to inefficient power management and potential logical errors due to insufficient capacitance and IR drops in the power delivery network, causing transistors to malfunction during high-power applications.

Innovation Solution

Implementing keephot instructions and cycles that allow processors to continuously consume power between mission cycles, mitigating power-load drops and rises by incrementally activating processor clusters, thereby reducing the severity of load steps and maintaining a constant voltage level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If processors execute instructions synchronously in lock step mode, then emulation accuracy is improved, but power consumption stability deteriorates due to sudden load steps

Engineering Contradiction:
Improveemulation accuracyVSAvoidpower consumption stability
Core Design Contradiction:
Measurement precisionVSStability of the object's composition

Solution Approach 1:

The system performs preliminary actions by executing keephot instructions before mission instructions to gradually warm up the power delivery network. This preliminary power consumption prevents sudden load steps when mission cycles begin, thereby maintaining both emulation accuracy and power stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The execution cycle is segmented into two distinct phases: keephot cycles that consume power to stabilize the power delivery network, and mission cycles that perform actual emulation work. This segmentation allows the system to separate power stabilization from computation, resolving the contradiction between accurate synchronous execution and stable power consumption.

Inventive Principle:
Principle #1Segmentation

2Stability of the object's composition

If capacitance is increased to compensate for voltage drops, then voltage stability is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage stabilityVSAvoidcapacitance configuration
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

Instead of relying on large capacitance to bridge gaps between execution cycles, the system maintains continuous useful action by executing keephot instructions that consume power continuously. This continuous power consumption eliminates voltage drops without requiring increased capacitance, thereby maintaining voltage stability while avoiding increased device complexity.

Inventive Principle:
Principle #20Continuity of useful action

3Use of energy by moving object

If processors are activated intermittently between mission cycles, then power efficiency is improved, but voltage fluctuations worsen due to load steps

Engineering Contradiction:
Improvepower efficiencyVSAvoidvoltage stability
Core Design Contradiction:
Use of energy by moving objectVSStability of the object's composition

Solution Approach 1:

The system maintains continuous power consumption through keephot instructions executed between mission cycles. This continuous action prevents the idle-to-active transitions that cause voltage fluctuations, while the keephot computations remain useful by maintaining processor warmth and readiness for subsequent mission cycles.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10386909B1Method and system to mitigate large power load steps due to intermittent execution in a computation system
Publication Date: 2019.08.20 CADENCE DESIGN SYST INC
  • US10386909B1 patent drawing
  • US10386909B1 patent drawing
  • US10386909B1 patent drawing

AI summary

Disclosed herein are systems and methods to generate, by a compiling processor, one or more sets of one or more execution instructions responsive to compiling a netlist file. The method further includes storing, by the compiling processor, a set of execution instructions into an instruction memory of an execution processor. The method further includes generating, by a compiling processor, a set of one or more keephot instructions for the execution processor based upon the set of execution instructions stored into the instruction memory of the execution processor. The method further includes storing, by a compiling processor, the set of keephot instructions into the instruction memory of the execution processor.