Kerf Alignment Mark Structure for CMP Dishing Suppression

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Solution Overview

Problem

Semiconductor devices face issues with dishing and film peeling during the manufacturing process, particularly in the kerf area where alignment marks are used, leading to potential defects in lithography and adhesion problems.

Innovation Solution

Incorporating a fine pattern in the kerf area with an interlayer insulating film, which acts as a stopper during chemical mechanical polishing (CMP) to reduce dishing and improve adhesion between layers, thereby stabilizing the alignment marks and preventing film peeling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If chemical mechanical polishing (CMP) is performed on the semiconductor substrate, then the surface flatness is improved, but dishing occurs in the kerf area

Engineering Contradiction:
Improvesurface flatnessVSAvoiddishing
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The patent applies local quality by providing a stopper structure specifically in the kerf area (non-memory cell regions) rather than uniformly across the entire substrate. The stopper has different properties than the surrounding film layers, creating localized variation that prevents dishing only where needed during CMP processing.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The stopper structure acts as an intermediary element between the CMP polishing surface and the underlying film layers. It mediates the polishing process by providing a controlled resistance to the polishing head, preventing excessive removal of material and thereby preventing dishing in the kerf area.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If the kerf area is left without additional structures, then the manufacturing process is simpler, but film peeling occurs during polishing

Engineering Contradiction:
Improveprocess simplicityVSAvoidadhesion
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The stopper structure is formed in advance during the film stacking process, before the CMP polishing step. This preliminary action ensures that the adhesion reinforcement is already in place to prevent film peeling during the subsequent polishing operation, without requiring additional process steps later.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If alignment marks are provided in the kerf area, then lithography alignment is improved, but the marks become unstable due to dishing and film peeling

Engineering Contradiction:
Improvealignment accuracyVSAvoidalignment mark stability
Core Design Contradiction:
Measurement precisionVSStability of the object's composition

Solution Approach 1:

The stopper structure provides beforehand cushioning by preventing dishing and film peeling in the kerf area where alignment marks are located. This protective action occurs before any potential damage to the alignment marks, ensuring their stability and maintaining their visibility and precision throughout the manufacturing process.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The fine pattern effectively reduces dishing and film peeling, enhancing the visibility and stability of alignment marks, thus improving the manufacturing process and reducing defects in semiconductor devices.

Implementation Method 1

acts as a stopper during chemical mechanical polishing (CMP)

Methodology Applied
Scientific EffectChemical Mechanical Polishing (CMP):

Data Source

PatentUS20230402395A1Semiconductor device
Publication Date: 2023.12.14 KIOXIA CORP
  • US20230402395A1 patent drawing
  • US20230402395A1 patent drawing
  • US20230402395A1 patent drawing

AI summary

A semiconductor device includes: a semiconductor substrate including a first area and a second area; a plurality of memory cells provided in the first area; a mark provided in the second area and having a first side surface and a second side surface that intersects with the first side surface; and a plurality of patterns provided in the second area and provided on the first side surface and the second side surface.