Kernel Computation Hardware Using Power-of-Two Coefficients
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Solution Overview
Problem
Existing digital signal processing techniques require significant gate-level resources for kernel computations in image processing applications, particularly when applying kernel matrices to large image sensors, leading to inefficient use of hardware and high clock cycle requirements.
Innovation Solution
The approach involves grouping similar kernel coefficients together, utilizing symmetric distributions of coefficients, and representing coefficients as powers of two to reduce the number of multipliers and adders needed, allowing for efficient kernel computations with reduced gate-level resources and clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional kernel computation methods are used, then accurate image processing is achieved, but gate-level resources (multipliers and adders) are excessively consumed
Solution Approach 1:
The patent transforms kernel coefficient values into exponent forms (powers of 2), changing the parameter representation from linear to exponential. This allows multiplication operations to be replaced with addition operations, significantly reducing the need for multipliers while maintaining processing accuracy.
Solution Approach 2:
The patent substitutes multiplication operations with addition operations by representing kernel coefficients as powers of 2. This mechanical substitution replaces complex multiplier circuits with simpler adder circuits, reducing gate-level resources while preserving the mathematical equivalence of the computation.
2Device complexity
If kernel computations are performed with reduced gate-level resources, then hardware efficiency is improved, but processing speed may be compromised
Solution Approach 1:
The patent implements a systematic approach where kernel coefficients are periodically represented as powers of 2, allowing the use of addition operations in regular intervals. This periodic transformation maintains processing speed by ensuring that critical path operations remain efficient while reducing overall resource requirements.
Solution Approach 2:
By changing the parameter representation of kernel coefficients to exponent forms, the patent enables faster addition-based computations compared to multiplication-based approaches, thereby maintaining or even improving processing speed while reducing hardware complexity.
3Productivity
If more multipliers and adders are used, then processing capability is enhanced, but manufacturing cost and device area increase
Solution Approach 1:
The patent extracts the essential computational function from complex multiplication operations and implements it through simpler addition operations. By taking out the multiplication requirement and replacing it with addition, the patent reduces manufacturing complexity and cost while preserving processing capability.
Solution Approach 2:
The patent uses simpler adder circuits instead of expensive multiplier circuits. Adders are cheaper and easier to manufacture, and by using multiple adders in sequence or parallel, the patent achieves the same processing capability at lower manufacturing cost and smaller device area.
Data Source
AI summary
A method and apparatus for efficiently performing digital signal processing is provided. In one embodiment, kernel matrix computations are simplified by grouping similar kernel coefficients together. Each coefficient group contains only coefficients having the same value. At least one of the coefficient groups has at least two coefficients. Techniques are disclosed herein to efficiently apply successive first order difference operations to a data signal. The techniques allow for a low gate count. In particular, the techniques allow for a reduction of the number of multipliers without increasing clock frequency, in an embodiment. The techniques update pixels of a data signal at a rate of two clock cycles per each pixel, in an embodiment. The techniques allow hardware that is used to process a first pixel to be re-used to start the processing of a second pixel while the first pixel is still being processed.