Kernel Space Interrupt Event Queue Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for communicating interrupts from kernel space ISRs to user space drivers suffer from high latency and excessive resource utilization, particularly when using RAM-based file systems or blocking system calls, and event queues with locks lead to inefficiencies.
Innovation Solution
Implement a method where ISRs in kernel space directly enqueue events onto event queues when possible, and only offload to a kernel helper thread when the event queue is unavailable, using separate event cores for different processing cores to minimize unavailability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ISRs use event queues with locks to communicate interrupts to user space, then interrupt handling capability is improved, but resource utilization increases due to locking overhead and potential context switching
Solution Approach 1:
The patent segments the event queue into multiple per-CPU event queues, where each CPU has its own dedicated event queue. This segmentation eliminates the need for a single global lock, allowing ISRs on different CPUs to enqueue events simultaneously without contention, thereby reducing locking overhead and improving resource utilization while maintaining interrupt handling capability
Solution Approach 2:
The patent introduces a hybrid mechanism as an intermediary between traditional locked event queues and direct ISR access. The mechanism uses a combination of lock-free direct access paths and fallback locked paths, allowing most operations to proceed without locks while providing safety mechanisms when needed, thus reducing resource utilization overhead
2Reliability
If ISRs loop until event queue is unlocked, then event enqueuing reliability is improved, but latency increases and resource utilization increases
Solution Approach 1:
The patent extracts the looping/waiting behavior from the ISR context and replaces it with direct enqueue operations on per-CPU queues. By removing the need for ISRs to loop or wait, the solution eliminates the associated latency and resource consumption while maintaining reliability through the per-CPU queue architecture that guarantees enqueue success
Solution Approach 2:
Each CPU serves its own event queue independently without requiring external locking or waiting mechanisms. The per-CPU queue design allows each ISR to self-service its dedicated queue without interfering with or being blocked by other CPUs, eliminating the need for reliability-critical looping while reducing latency
3Use of energy by moving object
If ISRs offload enqueuing to kernel space threads, then resource utilization is improved by allowing ISR to exit, but context switching overhead increases
Solution Approach 1:
The patent segments the event queue access into per-CPU dedicated queues, allowing ISRs to directly enqueue events without offloading to kernel threads. This segmentation eliminates the need for context switching between ISR and kernel thread contexts, reducing overhead while maintaining the ability to handle events efficiently in user space
4Use of energy by moving object
If polling is done infrequently to reduce resource utilization, then resource utilization is improved, but latency increases
Solution Approach 1:
The patent enables continuous event notification by having user space drivers register interest in specific event queues and receive notifications when events are enqueued. This continuous mechanism eliminates the need for periodic polling, maintaining low resource utilization while ensuring low latency through immediate notification of events
Data Source
AI summary
Techniques are provided for routinely enqueuing events onto event queues by direct operation of an interrupt service routine (ISR) in kernel space when possible. Only when the event queue is unavailable does the ISR resort to offloading the enqueuing process to another kernel space thread. Unavailability can further be made uncommon by using separate event cores for different processing cores.

