Kernel Placement in Programmable Logic via Dynamic Region Analysis

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Solution Overview

Problem

Inefficient placement of kernels in programmable logic of hardware accelerators leads to routing congestion and poor quality of results (QOR) due to inefficient use of memory resources, complicating the compilation process and developer productivity.

Innovation Solution

A method that compiles source code to generate logical circuit descriptions of kernel circuits, determines resource availability and utilization in dynamic regions of programmable logic, identifies optimal fitting solutions for kernel placement and memory connectivity, and generates a kernel image to implement kernel circuits and a memory subsystem, optimizing kernel placement and memory connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If kernels are placed in programmable logic without optimized placement algorithms, then the compilation process is simpler, but routing congestion occurs and quality of results deteriorates

Engineering Contradiction:

Improvequality of resultsVSAvoidcompilation process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary resource availability determination and kernel fitting solution identification before final kernel placement. The compilation process proactively analyzes resource constraints, determines optimal kernel placements, and generates placement configurations in advance, avoiding routing congestion and poor QOR before they occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary compilation process that acts as a mediator between kernel design and hardware deployment. This intermediary layer performs resource analysis, generates fitting solutions, and creates optimized placement configurations, resolving the conflict between simple placement and optimal QOR.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If kernels are placed without considering memory connectivity, then placement is faster, but memory resource efficiency decreases

Engineering Contradiction:

Improveplacement speedVSAvoidmemory resource efficiency

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent performs preliminary determination of resource availability and resource utilization by kernels before final placement. It identifies fitting solutions that consider both placement and memory connectivity together in advance, ensuring efficient memory resource utilization without sacrificing placement speed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameters considered during placement from simple location to comprehensive fitting solutions that include memory connectivity. By optimizing placement based on multiple parameters (resource availability, utilization, and connectivity), the system achieves both speed and efficiency.

Inventive Principle:

Principle #35Parameter changes

3Loss of time

If dynamic region resources are not analyzed before placement, then compilation is quicker, but routing congestion and poor QOR result

Engineering Contradiction:

Improvecompilation timeVSAvoidquality of results

Core Design Contradiction:

Loss of timeVSManufacturing precision

Solution Approach 1:

The patent performs preliminary resource availability determination in the dynamic region before kernel placement. It proactively identifies resource constraints and generates optimized fitting solutions, preventing routing congestion and poor QOR while minimizing additional compilation time through efficient algorithms.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11561779B1Applications for hardware accelerators in computing systems

Publication Date: 2023.01.24 XILINX INC

AI summary

An example method of implementing an application for a hardware accelerator having a programmable device coupled to memory is disclosed. The method includes compiling source code of the application to generate logical circuit descriptions of kernel circuits; determining resource availability in a dynamic region of programmable logic of the programmable device, the dynamic region exclusive of a static region of the programmable logic programmed with a host interface configured to interface a computing system having the hardware accelerator; determining resource utilization by the kernel circuits in the dynamic region; determining fitting solutions of the kernel circuits within the dynamic region, each of the fitting solutions defining connectivity of the kernel circuits to banks of the memory; adding a memory subsystem to the application based on a selected fitting solution of the fitting solutions; and generating a kernel image configured to program the dynamic region to implement the kernel circuits and the memory subsystem.