Neural Network Kernel Sequence Rearrangement for Processing Efficiency

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Solution Overview

Problem

Electronic devices face challenges in reducing the amount of operations required to process input data using neural networks, leading to increased processing time.

Innovation Solution

The electronic device includes a memory storing a neural network with multiple layers, each comprising kernels. A processor arranges the neural network by identifying the number of first weights for each kernel, determining the operation sequence turn for each kernel, and updating the sequence to optimize processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the neural network processes input data using a large number of operations, then the processing accuracy is maintained, but the processing time increases

Engineering Contradiction:
Improveprocessing accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing the number of first weights (zero values) for each kernel before actual neural network processing. This pre-computed information is then used to optimize the operation sequence during processing, allowing the system to skip unnecessary operations involving zero weights, thereby reducing processing time while maintaining accuracy

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the processing parameters by dynamically adjusting the operation sequence based on the distribution of zero weights in kernels. By identifying kernels with higher proportions of zero weights and processing them differently (skipping zero-weight operations), the system transforms the fixed processing approach into a variable one that adapts to the specific characteristics of each kernel, reducing overall processing time

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the neural network uses more kernels in each layer, then the processing capability is enhanced, but the computational complexity increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidcomputational complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by treating each kernel differently based on its specific characteristics, particularly the number and distribution of zero weights. Instead of applying a uniform processing approach to all kernels, the system identifies and processes kernels with different zero-weight densities using optimized sequences, reducing the computational complexity associated with processing capability enhancement

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If the neural network performs standard processing operations, then the implementation is straightforward, but the processing speed is limited

Engineering Contradiction:
Improveimplementation simplicityVSAvoidprocessing speed
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent implements preliminary action by pre-analyzing the weight distributions of all kernels and determining the optimal processing sequence before actual neural network inference. This pre-computed operation sequence information is stored and reused during processing, allowing the system to achieve faster processing speeds without complicating the actual implementation of processing operations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating and storing a separate data structure that contains the operation sequence information (turn values) for each kernel. This copied information is then referenced during processing to determine the optimal execution order, separating the complexity of sequence optimization from the actual processing implementation

Inventive Principle:
Principle #26Copying

Data Source

PatentUS12314831B2Electronic device for rearranging kernels of neural network and operating method thereof
Publication Date: 2025.05.27 SAMSUNG ELECTRONICS CO LTD
  • US12314831B2 patent drawing
  • US12314831B2 patent drawing
  • US12314831B2 patent drawing

AI summary

Disclosed is an electronic device may include a memory storing a neural network including a plurality of layers, each of the plurality of layers comprising a plurality of kernels, and at least one processor, wherein the at least one processor is configured to: arrange the neural network; and perform neural network processing on input data based on the arranged neural network, and wherein the arranging the neural network includes: with respect to each of the plurality of layers of the neural network, identifying a number of first weights of each of a plurality of kernels included in a layer; identifying a turn that each of the plurality of kernels included in the layer has in an operation sequence based on the identified number of first weights; and updating the turn that each of the plurality of kernels has in the operation sequence based on the identified turn for each of the plurality of kernels.