Inter-Kernel Stall Signaling for FIFO Deadlock Detection
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Solution Overview
Problem
Deadlocks in integrated circuits due to FIFO channel sizing errors and data rate mismatches are difficult to detect and diagnose, leading to system halts.
Innovation Solution
Implement additional circuitry in the design to generate signals indicating kernel stalls, use EDA systems for HDL simulation and hardware prototyping to detect deadlocks, and adjust FIFO channel sizes to prevent errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuitry is added to detect kernel stalls and deadlocks, then deadlock detection capability is improved, but device complexity increases
Solution Approach 1:
The design is divided into multiple kernels, each independently monitored for stall conditions. Each kernel has its own stall detection mechanism that independently generates signals when stalling occurs, allowing distributed deadlock detection without requiring a centralized complex monitoring system.
Solution Approach 2:
Stall detection signals act as intermediaries between the kernel processes and the deadlock detection logic. These signals mediate the information flow, allowing the system to detect deadlocks by monitoring the presence of stall signals from multiple kernels without requiring direct observation of internal process states.
2Reliability
If FIFO channel sizes are increased to prevent deadlocks, then system reliability is improved, but loss of time due to waiting increases
Solution Approach 1:
The system performs preliminary deadlock detection by monitoring stall signals before actual deadlocks occur. By detecting potential deadlock conditions early through stall signal analysis, the system can take corrective actions or adjust FIFO sizes proactively, preventing system halts without requiring excessively large FIFO buffers that would increase waiting time.
Solution Approach 2:
The deadlock detection mechanism provides feedback about stall conditions to the system controller. This feedback enables dynamic adjustment of FIFO channel sizes based on actual runtime conditions, allowing the system to maintain reliability while minimizing waiting time by sizing FIFOs appropriately rather than using oversized buffers.
Data Source
AI summary
Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.