Processor Kernel Trace Profiling for Secure IC Debugging

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Solution Overview

Problem

Modern integrated circuits (ICs) face challenges in implementing event trace and profiling for data processing arrays due to security concerns, which prevent host systems from directly accessing and configuring certain compute circuits.

Innovation Solution

The method involves executing kernels in the processor system of an IC to receive and apply configuration data for trace or profiling functions on active tiles of the data processing array, generating trace or profiling data, and providing this data to the host data processing system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the host system directly accesses and configures compute circuits for trace and profiling, then ease of operation is improved, but security is worsened

Engineering Contradiction:
Improveease of operationVSAvoidsecurity
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary mechanism where the host system communicates trace and profiling configuration requests to the compute circuit through a controlled interface. The compute circuit receives high-level commands from the host system but maintains independent control over its internal trace and profiling functions, preventing direct host access while enabling operational control. This resolves the contradiction by allowing ease of operation through host-initiated commands while maintaining security through the compute circuit's autonomous configuration management.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the host system is prevented from directly accessing compute circuits, then security is improved, but ease of operation is worsened

Engineering Contradiction:
ImprovesecurityVSAvoidease of operation
Core Design Contradiction:
Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The compute circuit is designed with self-service capabilities to perform trace and profiling operations autonomously based on high-level commands from the host system. The compute circuit independently configures its own trace and profiling functions, manages data collection, and controls data transfer to host memory, eliminating the need for direct host access to compute circuit resources. This maintains security through access prevention while preserving ease of operation through automated self-configuration and execution.

Inventive Principle:
Principle #25Self-service

3Object-affected harmful factors

If indirect control mechanisms are used for trace and profiling, then security is improved, but device complexity is worsened

Engineering Contradiction:
ImprovesecurityVSAvoiddevice complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The compute circuit integrates multiple functions including computation, trace, profiling, and data management within a single autonomous unit. The same compute circuit that performs user computations also independently handles trace and profiling operations based on host commands, eliminating the need for separate dedicated hardware interfaces or control mechanisms. This multi-functionality reduces overall device complexity while maintaining security through the unified autonomous control architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12314735B2Data processing array event trace and profiling using processor system executed kernels
Publication Date: 2025.05.27 XILINX INC
  • US12314735B2 patent drawing
  • US12314735B2 patent drawing
  • US12314735B2 patent drawing

AI summary

Within an integrated circuit including a processor system and a data processing array, one or more kernels in the processor system are executed in response to a scheduling request from a host data processing system. The one or more kernels receive configuration data for implementing trace or profiling of a user design executable by a plurality of active tiles of the data processing array. Using the one or more kernels, selected tiles of the plurality of active tiles of the data processing array are configured with the configuration data to perform the trace or the profiling. Trace data or profiling data is generated through execution of the user design by the data processing array. The one or more kernels provide the trace data or the profiling data to the host data processing system.