Kernel User Space Memory Management via Separate Page Tables
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Solution Overview
Problem
Conventional memory management in computers does not efficiently utilize memory space and raises security concerns, as the operating system kernel and user processes share the same page tables, making it vulnerable to malware and lacking features like the No-eXecute bit for enhanced virus protection.
Innovation Solution
Implementing separate root page table indices for the kernel and user spaces, allowing for dedicated virtual-to-physical address translations, which enhances memory usage and security by isolating memory access and enabling features like the No-eXecute bit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the OS kernel and user processes share the same page tables, then memory space utilization is improved, but security is worsened
Solution Approach 1:
The patent divides the previously unified page table into separate page tables for kernel space and user space. The CPU is enhanced with multiple CR3 registers (CR3K for kernel, CR3U for user) that can be independently switched, creating distinct memory management segments. This segmentation isolates kernel and user memory accesses, preventing user processes from corrupting kernel page tables while maintaining efficient memory utilization through separate virtual-to-physical address translation paths.
2Reliability
If separate page tables are used for kernel and user spaces, then security is improved, but device complexity is worsened
Solution Approach 1:
The patent implements automatic context switching between kernel and user page tables through hardware-supported CR3 register management. When the CPU transitions between kernel mode and user mode, the appropriate CR3 register is automatically selected and updated with the corresponding root page table index. This self-service mechanism eliminates the need for complex software page table switching logic, reducing the actual operational complexity despite the enhanced security architecture.
3Ease of operation
If common page tables are used among OS kernel and user processes, then ease of operation is improved, but vulnerability to malware is worsened
Solution Approach 1:
The patent introduces separate CR3K and CR3U registers as intermediaries between the CPU and the page table structures. These registers act as dedicated gateways that route kernel address translations through CR3K and user address translations through CR3U, each pointing to their respective root page tables. This intermediary mechanism maintains simple memory access operations while physically isolating kernel and user memory spaces, preventing malware in user space from exploiting shared page table vulnerabilities.
4Adaptability or versatility
If a 32-bit page table entry format is used, then compatibility is maintained, but adaptability to emerging features is worsened
Solution Approach 1:
The patent employs a multi-level page table structure where 32-bit page table entries are nested within a hierarchical translation system. The virtual address is divided into multiple segments that traverse through page directories and page tables, with each level providing translation granularity. This nesting allows the system to maintain compatibility with traditional 32-bit entry formats while utilizing the combined addressing capacity of multiple levels, creating room for emerging features like the No-eXecute (NX) bit without sacrificing address translation capacity.
Data Source
AI summary
The present application provides methods and systems for memory management of a kernel space and a user space. An exemplary system for memory management of the kernel space and the user space may include a first storing unit configured to store a first root page table index corresponding to the kernel space. The system may also include a second storing unit configured to store a second root page table index corresponding to the user space. The system may further include a control unit communicatively coupled to the first and second registers and configured to: translate a first virtual address to a first physical address in accordance with the first root page table index for an operating system kernel, and translate a second virtual address to a second physical address in accordance with the second root page table index for a user process.