Key-Based Data Word Ordering Circuit for Low-Latency Sorting
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Solution Overview
Problem
Existing circuits for key-based sorting in high-bandwidth data communication require substantial logic and have latency issues, failing to achieve targeted low latency and high bandwidth simultaneously.
Innovation Solution
A circuit that uses a memory to receive keys and provide ordered sets of identifiers, with multiplexers selecting data words based on these identifiers, allowing for fast parallel ordering of data words in a single clock cycle, reducing the need for extensive logic and optimizing latency and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated circuits are used for key-based sorting, then sorting functionality is achieved, but the amount of logic required becomes substantial
Solution Approach 1:
The sorting function is segmented into two independent parts: a memory unit that stores pre-computed permutation patterns, and a multiplexer unit that performs the actual data reordering. This segmentation eliminates the need for complex sorting logic within a single circuit, as the memory stores the sorting decisions and the multiplexer simply executes them.
Solution Approach 2:
The sorting permutations are pre-computed and stored in the memory unit before the actual sorting operation. When sorting is needed, the system only needs to retrieve the pre-stored permutation pattern corresponding to the input keys and apply it via the multiplexer, rather than computing the sorting logic in real-time.
2Productivity
If pipeline stages are added to achieve targeted bandwidth, then throughput increases, but latency becomes greater than targeted latency
Solution Approach 1:
The memory unit continuously provides the next permutation pattern while the multiplexer is still applying the current pattern to data. This overlapping of operations ensures that the sorting function is always ready to process the next set of data without waiting for the current operation to complete, maintaining continuous useful action.
Solution Approach 2:
The permutation patterns are pre-computed and stored in the memory unit, so when data arrives for sorting, the corresponding permutation pattern is already available in the memory. This eliminates the need for runtime computation of sorting logic, reducing latency while maintaining high throughput.
3Measurement precision
If more logic is used in sorting circuits, then sorting accuracy improves, but bandwidth decreases
Solution Approach 1:
The complex mechanical/logic-based sorting computation is replaced by a memory lookup operation. Instead of using logic circuits to compare and swap elements, the system stores pre-computed swap sequences in memory and retrieves them based on the input keys, substituting computational logic with memory access.
Solution Approach 2:
The sorting function is divided into memory storage of permutation patterns and multiplexer execution. This segmentation allows the system to achieve high sorting accuracy through pre-computed patterns while maintaining high bandwidth through efficient memory access and parallel multiplexer operation.
Data Source
AI summary
Quick key-based ordering of data words is provided. A memory is arranged to receive the keys at an address input port. The memory is adapted to provide at a data output port one of a plurality of ordered sets of identifiers. Each key is associated with a respective one of the data words and each identifier of the one of the ordered sets identifies a respective one of the data words. Each of a plurality of multiplexers is arranged to receive a respective identifier of the one of the ordered sets from the memory and to receive the data words. Each multiplexer is adapted to select the respective one of the data words identified by the respective identifier. A program storage medium may be configured with instructions to perform operations including generating configuration data for a programmable device. The configuration data may implement the memory and the multiplexers.