Key Generation Unit Physical Unclonable Function Scan Timing

The patent extracts the key generation function from the original combinational logic circuit path and relocates it to a separate key generation unit. The original combinational logic circuits are removed from between the scanning flip-flops, while a new key generation unit is introduced that uses the same combinational logic circuits but in a different configuration that does not interfere with scan verification timing.

The patent segments the circuit functionality by separating the scan verification path from the key generation path. The scanning flip-flops remain dedicated to scan verification, while a separate key generation unit utilizes the combinational logic circuits to generate keys. This segmentation allows both functions to operate independently without timing conflicts.

The patent introduces a key generation unit as an intermediary component that mediates between the combinational logic circuits and the scanning flip-flops. This intermediary unit captures the output of the combinational logic circuits at appropriate timing points and stores it in dedicated storage elements, preventing direct interference with the scan verification timing while still enabling key generation.

The patent performs preliminary action by capturing the combinational logic circuit outputs at specific timing points before they can affect the scan verification process. The key generation unit samples and stores these outputs during initialization or setup phases, ensuring that the scan verification timing remains unaffected during normal operation.