Semiconductor Key Region Structure for Dense Pattern Overlay Metrology
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Solution Overview
Problem
The increasing integration density and complexity of semiconductor devices pose challenges in accurately forming patterns at desired positions during fabrication, affecting reliability and performance.
Innovation Solution
A semiconductor device design incorporating a substrate with key regions, dummy active and channel patterns, and epitaxial patterns, along with specific sub-key patterns, and a method involving alternately stacking active and sacrificial layers to form recesses and replace sacrificial patterns with sub-key patterns, enhancing overlay measurement precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integration density is increased, then device functionality and performance are improved, but manufacturing precision and pattern alignment become more difficult to achieve
Solution Approach 1:
The patent introduces a key pattern structure as an intermediary element between different fabrication layers. This key pattern includes a key hole region with specific optical properties that serves as a reference marker for overlay measurement, enabling precise alignment between layers despite increased device complexity and integration density.
Solution Approach 2:
The patent replaces traditional mechanical alignment methods with optical-based overlay measurement. By incorporating the key pattern with key hole regions that interact with measurement light, the system uses optical effects rather than mechanical positioning to achieve precise pattern alignment during fabrication.
2Adaptability or versatility
If structural complexity is increased to meet performance demands, then device performance is improved, but fabrication accuracy deteriorates
Solution Approach 1:
The key pattern structure acts as an intermediary reference system that simplifies the fabrication process. By providing dedicated key hole regions for overlay measurement, it enables accurate pattern formation even as the overall device structure becomes more complex to achieve higher performance.
Solution Approach 2:
The patent utilizes optical properties (analogous to color changes) of the key hole regions in the key pattern. These regions are designed to interact with measurement light in specific ways, allowing optical detection systems to accurately determine alignment status during fabrication, thereby maintaining fabrication accuracy despite increased structural complexity.
3Productivity
If pattern density is increased, then integration density is improved, but overlay measurement precision becomes more challenging
Solution Approach 1:
The key pattern introduces dedicated intermediary reference structures (key hole regions) that are separate from the high-density device patterns. These key holes provide clear, unambiguous reference points for overlay measurement, enabling precise alignment measurement even when the actual device patterns are densely packed and difficult to measure.
Solution Approach 2:
The patent segments the measurement function from the device structure by creating separate key pattern regions with key holes. This segmentation allows the measurement system to focus on these dedicated reference regions rather than attempting to measure the complex, high-density device patterns directly, thereby maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the reliability and performance of semiconductor devices by enabling precise pattern formation and alignment, supporting high integration density and multiple functions.
Implementation Method 1
forming an epitaxial pattern in the recess
Data Source
AI summary
A semiconductor device includes a substrate including a key region, a dummy active pattern provided on the key region, a dummy channel pattern provided on the dummy active pattern, the dummy channel pattern including a first plurality of semiconductor patterns spaced apart from each other, an epitaxial pattern connected to the dummy channel pattern, and a first sub-key pattern provided on the dummy channel pattern. The first sub-key pattern encloses a top surface, a bottom surface, and side surfaces of each of the first plurality of semiconductor patterns.