Key Scheduling Device Parallel Verification Circuit
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Solution Overview
Problem
Existing encryption and decryption devices face challenges in achieving high processing speeds and small sizes due to the need for a register to store expanded keys for verification, which hinders circuit miniaturization and increases overhead in error detection processes.
Innovation Solution
The implementation of a key scheduling device with a non-linear transformation unit and a linear transformation circuit that allows for the generation and verification of expanded keys in parallel, reducing the need for separate storage registers and enabling efficient error detection without increasing input bit length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a register is provided to store expanded keys for verification, then verification capability is improved, but device size increases
Solution Approach 1:
The patent merges the verification function into the existing key scheduler structure by using the same expanded key register for both encryption/decryption operations and verification operations. The verification is performed by reusing the expanded keys that are already stored in the register, eliminating the need for separate verification registers and reducing overall circuit size while maintaining verification capability.
Solution Approach 2:
The expanded key register is designed to serve multiple functions: storing expanded keys for encryption/decryption operations and simultaneously providing keys for verification operations. This multi-functional approach allows the same hardware resource to support both primary encryption functions and error detection functions without requiring additional dedicated storage resources.
2Productivity
If verification is performed in parallel with arithmetic operations, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent combines verification operations with the existing key scheduling arithmetic operations by performing verification in the same time cycle. The verification unit operates in parallel with the key scheduler, using the same expanded keys and performing verification calculations simultaneously with encryption/decryption operations, thereby achieving high processing speed without requiring completely separate verification hardware.
Solution Approach 2:
The verification process is prepared in advance by pre-computing verification keys and preparing verification circuits that can operate immediately when needed. The verification unit is pre-configured with the same expanded key generation logic, allowing it to perform verification operations in parallel with encryption/decryption without requiring additional real-time computational resources.
Data Source
AI summary
According to one embodiment, in a key scheduling device, a non-linear transformation unit non-linearly transforms at least one of partial keys resulting from dividing an expanded key. A first linear transformation unit includes first and second circuits. The second circuit linearly transforms the partial key by directly using a transformation result from the non-linear transformation unit. A first storage stores the partial key linearly transformed by the first linear transformation unit. A second linear transformation unit linearly transforms, inversely to the first linear transformation unit, each of partial keys other than the partial key linearly transformed by the second circuit out of the partial keys stored in the first storage, and outputs inversely transformed partial keys. A second storage stores one of inputs to the second circuit. An outputting unit connects the respective inversely transformed partial keys and the input stored in the second storage to be output as a second key.