Key Storage Device Using Asymmetric Threshold Voltages

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces the threat of reverse engineering of integrated circuits (ICs), which can lead to unauthorized reproduction and theft of circuit designs, necessitating a mechanism to provide keys for preventing such unauthorized access.

Innovation Solution

A key storage device comprising a first and second key unit, each with a setting circuit and an inverter, where the first threshold voltage is lower than the second threshold voltage, and the first setting voltage is higher than the second setting voltage, to generate distinct logic values, thereby preventing reverse engineering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional key storage methods are used, then the circuit design can be implemented, but the IC becomes vulnerable to reverse engineering and unauthorized reproduction

Engineering Contradiction:
Improvesecurity against reverse engineeringVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating key units with distinct local characteristics - each key unit contains transistors with specific threshold voltages (first threshold voltage for first key unit, second threshold voltage for second key unit) that differ from each other. This local differentiation in transistor parameters enables the generation of unique key values at different nodes, providing security against reverse engineering while maintaining a relatively simple overall circuit structure

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs asymmetry by designing key units with intentionally asymmetric parameters - the first and second key units have different threshold voltages, and the first and second nodes operate at different voltage levels. This asymmetric design ensures that even if one key unit is reverse engineered, the different parameters make it difficult to predict or replicate the keys from other key units, thereby enhancing security

Inventive Principle:
Principle #4Asymmetry

2Reliability

If multiple key units with different parameters are implemented, then security against reverse engineering is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvesecurity against reverse engineeringVSAvoidthreshold voltage control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by pre-establishing the different threshold voltage parameters in the transistor design stage. The first and second key units are designed with predetermined threshold voltage differences before manufacturing, and the circuit is configured to operate with these pre-set parameter variations. This preliminary establishment of parameter differences simplifies the manufacturing process compared to requiring precise post-manufacturing adjustment, while still achieving the security goal of having distinct key parameters

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11961567B2Key storage device and key generation method
Publication Date: 2024.04.16 PUFSECURITY CORP
  • US11961567B2 patent drawing
  • US11961567B2 patent drawing
  • US11961567B2 patent drawing

AI summary

A key storage device comprising a first key unit and a second key unit is disclosed. The first key unit is configured to output a first logic value through, comprising: a first setting circuit configured to output a first setting voltage; and a first inverter comprising a first output transistor having a first threshold voltage, configured to receive the first setting voltage and generate the first logic value. The second key unit is configured to output a second logic value through a second node, comprising: a second setting circuit configured to output a second setting voltage; and a second inverter comprising a second output transistor having a second threshold voltage, configured to receive the second setting voltage and generate the second logic value. The absolute value of first threshold voltage is lower than which of the second threshold voltage. The first setting voltage is higher than the second setting voltage.