Wafer Level KGU Integration via Redistribution Layer and Wire Bond
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Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in achieving faster, more reliable, and higher-density integrated circuits at lower costs, particularly in integrating multiple semiconductor devices and components at the wafer level while maintaining efficient electrical and mechanical interconnects.
Innovation Solution
The method involves providing a substrate with an active surface and forming an adhesive layer to mount a known good unit (KGU), creating interconnect structures through wire bonding, redistribution layers, and forming solder bumps to connect the KGU and active circuits, allowing for efficient electrical connections and simplified substrate design by leveraging pre-packaged functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level integration of multiple semiconductor devices and components is achieved, then circuit density and performance are improved, but manufacturing complexity and difficulty of maintaining efficient interconnects increase
Solution Approach 1:
The patent segments the interconnect structure into distinct functional components: wire bonds for initial electrical connection, redistribution layers for signal routing, through-hole vias for vertical connectivity, and solder bumps for final attachment. This segmentation allows each component to be optimized independently while maintaining overall system complexity at manageable levels.
Solution Approach 2:
The patent transitions from planar two-dimensional circuit layouts to three-dimensional vertical stacking by implementing through-hole vias that penetrate the substrate and multiple redistribution layers at different heights. This dimensional change enables higher circuit density without proportionally increasing manufacturing complexity, as the vertical dimension provides additional routing space.
2Reliability
If pre-packaged known good units are integrated at wafer level, then reliability is improved, but substrate design complexity increases
Solution Approach 1:
The patent introduces an intermediary substrate that mediates between the pre-packaged known good units and the final circuit assembly. The substrate provides standardized mounting interfaces and interconnect structures that simplify the integration process, allowing reliable attachment of pre-packaged components without requiring complex custom substrate designs for each integration scenario.
Solution Approach 2:
The substrate design incorporates universal features including standardized adhesive layers for mounting, generic wire bond attachment points, and configurable redistribution layers that can accommodate different known good unit configurations. This universality reduces substrate design complexity by providing a reusable platform that works across multiple integration scenarios.
3Reliability
If multiple interconnect structures are formed for electrical connection, then circuit performance is improved, but manufacturing steps and time increase
Solution Approach 1:
The patent implements preliminary action by pre-forming wire bonds and attaching known good units to the substrate before final assembly. The wire bonds are established in advance, and the redistribution layers are prepared beforehand, allowing subsequent steps to proceed more quickly. This preliminary preparation reduces overall manufacturing time despite the multiple interconnect structures required.
Solution Approach 2:
The patent merges multiple manufacturing operations into combined process steps where possible. For example, the formation of through-hole vias is combined with the creation of redistribution layer contact points, and the attachment of solder bumps is integrated with the final assembly process. This merging reduces the total number of discrete manufacturing steps and decreases overall production time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor packages with improved performance, reduced signal propagation, and increased density by integrating pre-packaged components directly into the wafer level, thereby simplifying the substrate design and enhancing overall circuit performance.
Implementation Method 1
forming an adhesive layer over the active surface of the substrate, mounting a known good unit (KGU) to the adhesive layer
Implementation Method 2
providing a wire bond between a contact pad on the substrate and a contact pad on the KGU
Implementation Method 3
forming solder bumps in electrical contact with the redistribution layer
Data Source
AI summary
In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits on the substrate. The interconnect structure includes a wire bond between a contact pad on the substrate and a contact pad on the KGU, a redistribution layer on a back surface of the substrate, opposite the active surface, a through hole via (THV) through the substrate that electrically connects the redistribution layer and wire bond, and solder bumps formed in electrical contact with the redistribution layer. The KGU includes a KGU substrate for supporting the KGU, a semiconductor die disposed over the KGU substrate, and an encapsulant formed over the semiconductor die.