QC-LDPC Khatri-Rao Lifting for 7776-Bit 1/2-Rate Coding
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Solution Overview
Problem
Existing wireless communication standards, such as IEEE 802.11n-802.11be, are limited by a maximum block length of 1944 bits for LDPC codes, which restricts the gain in radio channels, particularly in multiple-input and multiple-output channels, and require computationally intensive encoding due to high-density generator matrices.
Innovation Solution
Implementing a quasi-cyclic low-density parity-check (QC-LDPC) code with a block length of 7776 bits and a code rate of ½, utilizing a parity check matrix with a quasi-cyclic structure and Khatri-Rao lifting to generate efficient encoding and decoding processes, allowing for parallel decoding and re-use of existing circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a maximum block length of 1944 bits is used for LDPC codes as per existing wireless communication standards, then device complexity is reduced and existing circuitry can be used, but radio channel performance gain is limited particularly in MIMO channels
Solution Approach 1:
The patent changes the block length parameter from the standard maximum of 1944 bits to 7776 bits (4x longer), and modifies the code rate parameter to achieve optimal performance in MIMO channels. This parameter change enables longer codewords that provide better error correction capability and radio channel performance gain while maintaining compatibility with existing QC-LDPC code structures
Solution Approach 2:
The patent segments the encoding process by using a base matrix that can be lifted to create the full parity check matrix. This segmentation allows the use of existing circuitry for the base operations while extending functionality to handle longer block lengths through systematic matrix construction and reuse of computational blocks
2Adaptability or versatility
If high-density generator matrices are used for encoding, then code rate flexibility is improved, but computational complexity increases making the encoding process intensive
Solution Approach 1:
The patent changes from high-density generator matrices to low-density parity check matrices where the density is controlled by the parameter ε (epsilon). By setting ε to specific values (e.g., ε=1/4 or ε=1/6), the patent achieves both code rate flexibility and reduced computational complexity, as the low-density structure enables efficient belief propagation decoding algorithms
Solution Approach 2:
The patent introduces dynamic adaptability by allowing the code rate to be adjusted through parameter selection (ε values) and block length scaling. The systematic structure of the parity check matrix allows dynamic configuration of code rates while maintaining efficient encoding and decoding operations through the quasi-cyclic property
3Productivity
If block length is extended to 7776 bits using QC-LDPC codes, then radio channel performance gain is improved and more information bits can be transmitted, but existing circuitry cannot be directly used without modification
Solution Approach 1:
The patent implements nesting by creating a hierarchical structure where a base matrix is embedded and lifted to form the full parity check matrix for longer block lengths. The base matrix operations can be performed by existing circuitry, while the lifting process systematically expands to 7776 bits using repeated patterns and structured extensions, allowing existing circuitry to be reused at multiple levels of the hierarchy
Solution Approach 2:
The patent achieves universality by designing a QC-LDPC code structure that can handle multiple block lengths (1944, 3888, 7776 bits) and multiple code rates through parameter adjustment. The same fundamental encoding and decoding circuitry can be configured to operate with different parameters, making the system multi-functional and adaptable to various transmission requirements without requiring completely different hardware for each configuration
Data Source
AI summary
An apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, based at least on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate R of ½, a second parity check matrix for a second QC-LDPC code, wherein the second QC-LDPC code has a code block size that is four times a code block size of the first QC-LDPC code. The one or more processors may be configured to encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data. In some implementations, the code block size of the second QC-LDPC code may be 7776 bits.