Kinked Polysilicon Structure for Memory Cell RSB Failure Reduction
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Solution Overview
Problem
Conventional memory device manufacturing techniques often result in random single bit (RSB) failures due to impurities, particles, and weak oxide residues, leading to shorts and increased failure rates.
Innovation Solution
The method involves forming memory cells with a kinked polysilicon profile and hard mask pull-back, which includes etching the polysilicon layer to create apertures and using high-density plasma oxide fill-in, combined with chemical mechanical polishing to minimize the likelihood of voids and shorts by ensuring a narrower top portion of the polysilicon layer's side surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory device manufacturing techniques are used, then manufacturing simplicity is maintained, but RSB failures increase due to particles, impurities, and weak oxide residues
Solution Approach 1:
The patent segments the polysilicon layer into multiple portions with different widths. The first polysilicon layer has a first width and the second polysilicon layer has a second width that is less than the first width, creating a stepped structure. This segmentation prevents particles and impurities from creating continuous leakage paths through the entire polysilicon structure, thereby reducing RSB failures while maintaining a manageable manufacturing process
Solution Approach 2:
The patent applies local quality by creating regions with different polysilicon layer widths at specific locations. The narrower second polysilicon layer is positioned at critical areas where leakage paths are most likely to occur, providing enhanced local protection against RSB failures caused by particles and impurities, while the wider first polysilicon layer maintains overall device functionality
2Reliability
If the polysilicon layer is made uniform in width, then manufacturing is simpler, but leakage paths may form between the polysilicon layer and substrate
Solution Approach 1:
The polysilicon layer is divided into segments with different widths - a first polysilicon layer with width W1 and a second polysilicon layer with width W2 < W1. This segmentation creates discontinuities that break potential leakage paths, preventing direct contact between conductive layers and the substrate even when manufacturing variations occur
Solution Approach 2:
The patent performs preliminary patterning to create the stepped polysilicon structure before final device assembly. By pre-establishing the narrower second polysilicon layer region, the design proactively prevents leakage paths from forming, rather than attempting to correct them after manufacturing variations occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces RSB failures by enhancing HDP oxide layer fill-in and preventing polysilicon layer shorts, thereby improving the reliability of memory devices.
Implementation Method 1
high-density plasma oxide fill-in
Implementation Method 2
chemical mechanical polishing
Data Source
AI summary
A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.