KR-Matrix Block Coding for Adjacent Bit Error Correction
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Solution Overview
Problem
As memory bit cells in integrated circuits (ICs) become smaller and denser, the likelihood of Single Event Upsets (SEUs) impacting multiple cells increases, while the demand for memory bandwidth also grows, posing a challenge for Error-Correcting Codes (ECC) to effectively detect and correct errors without hindering bandwidth demands.
Innovation Solution
The implementation of a Kumar-Rahul Code (KR-Matrix) that generates and decodes parity bits to detect and correct single, double, and triple adjacent bit errors, using a matrix format with a 1-to-1 ratio of occupied to unoccupied cells, allowing for efficient error detection and correction while maintaining memory bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more parity bits are added to resolve data corruption issues through ECC, then error correction capability is improved, but memory bandwidth is reduced
Solution Approach 1:
The patent changes the structural parameters of the parity bit arrangement by using a KR-Matrix format that doubles the number of rows while maintaining the same number of columns compared to traditional Hamming Code. This reconfiguration allows the same error correction capability to be achieved with a different bit distribution pattern, optimizing the balance between error correction and bandwidth utilization.
Solution Approach 2:
The patent transitions from a traditional linear arrangement of data and parity bits to a two-dimensional matrix structure (KR-Matrix). This dimensional change enables more efficient packing and arrangement of bits, allowing the system to maintain error correction capability while reducing the overhead impact on memory bandwidth through optimized spatial distribution.
2Quantity of substance
If memory bit cells are made smaller and denser, then storage capacity is improved, but susceptibility to Single Event Upsets increases
Solution Approach 1:
The patent applies local quality by distributing data bits throughout the matrix in an out-of-sequence order rather than contiguous arrangement. This local redistribution ensures that adjacent physical bit cells (which are more susceptible to SEUs due to proximity) are not necessarily adjacent in the logical matrix structure, thereby reducing the impact of localized SEU events while maintaining high storage density.
Solution Approach 2:
The patent segments the data and parity bits into a structured matrix format with specific row and column assignments. This segmentation allows the error correction mechanism to independently analyze and correct errors in different segments of the data, improving overall reliability against SEUs while maintaining compact storage.
3Reliability
If traditional Hamming Code configuration is used, then error detection and correction is achieved, but the ratio of occupied to unoccupied cells is not optimized
Solution Approach 1:
The patent introduces asymmetry in the matrix structure by doubling the number of rows while keeping the column count the same as traditional Hamming Code, creating a non-square matrix format. This asymmetric configuration optimizes the utilization of matrix cells by approximately achieving a 1-to-1 ratio of occupied to unoccupied cells, improving space efficiency while maintaining the error detection and correction capabilities.
Data Source
AI summary
An encoder block to receive input data has a KR-Matrix block. The KR-Matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n−1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n−1) parity bits to generate an (n) parity bit.