KV Cache Block Quantization for Longer Context on Limited Memory

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Solution Overview

Problem

Transformer-based generative models face memory resource constraints due to large context lengths, leading to inaccurate outputs and hardware resource scaling impracticality.

Innovation Solution

Optimize memory usage by implementing block-based quantization of the KV cache during runtime, specifically for the Key and Value matrices, allowing efficient storage and retrieval of values in SRAM and DRAM.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the context length is increased to maintain accurate outputs, then the model's reliability is improved, but the memory resources required increase significantly

Engineering Contradiction:
Improveoutput accuracyVSAvoidmemory resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies parameter changes by transitioning from full-precision floating-point representation to quantized integer representation (e.g., 4-bit or 8-bit integers) for storing KV cache data. This changes the data representation parameter to reduce memory requirements while maintaining sufficient precision for accurate model outputs, thus resolving the contradiction between context length and memory resources.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the KV cache into blocks that can be independently quantized and managed. By dividing the large KV cache into smaller quantized blocks, the system can efficiently manage memory resources while maintaining the ability to store extensive context lengths, resolving the contradiction between reliability and memory quantity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If hardware resources are scaled up to accommodate larger models, then the model's computational capability is improved, but the device complexity and cost increase

Engineering Contradiction:
Improvecomputational capabilityVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the data type parameter from high-precision floating-point to low-precision quantized integers, significantly reducing the memory bandwidth and computational requirements. This allows existing hardware with limited resources to execute large models effectively, reducing device complexity while maintaining computational capability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses quantized integer representations that are cheaper and more memory-efficient than full-precision floating-point numbers. These quantized representations act as simplified substitutes that maintain sufficient computational functionality while dramatically reducing hardware resource requirements.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Productivity

If the KV cache is stored in high-speed memory to reduce latency, then the model's throughput is improved, but the memory capacity is limited

Engineering Contradiction:
ImprovethroughputVSAvoidmemory capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent changes the data representation parameter to quantized integers, which require significantly less memory space. This enables the system to store larger portions of the KV cache in high-speed memory, increasing both the effective memory capacity for context and the throughput performance simultaneously.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12554398B2KV cache block-quantization oriented data handling
Publication Date: 2026.02.17 MICROSOFT TECHNOLOGY LICENSING LLC
  • US12554398B2 patent drawing
  • US12554398B2 patent drawing
  • US12554398B2 patent drawing

AI summary

A computing system for performing runtime data handling optimization for generative models is provided. The computing system comprises at least one processor and memory comprising a first memory and a second memory, wherein the memory stores instructions that, when executed by the at least one processor, cause the at least one processor to execute a generative model. The computing system computes a first value matrix entry based upon the processing of an input to the generative model. The first value matrix entry is stored in a first memory wherein a first group of value matrix entries is identified. The computing system executes data quantization on the first group of value matrix entries which results in a first quantized value matrix. The first quantized value matrix is added to a second memory where it can be used during generation of the generative model. When the first group of value matrix entries is less than a group size parameter, data padding matrix values are generated and used during execution of the data quantization.