KV Storage ECC Parity Allocation for Lower-Latency Error Correction
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Solution Overview
Problem
Key-Value (KV) databases in data storage devices face inefficiencies due to the need for translation layers and complex transaction mapping, leading to increased latency, power consumption, and reduced performance in data storage operations.
Innovation Solution
A data storage controller with an error correction code (ECC) engine and flash translation layer (FTL) that separates data into sub-code blocks and allocates parity bits, enabling asymmetric ECC coding and spatially-coupled LDPC coding to improve data storage efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a translation layer is used to map key/value to block storage, then data can be stored in traditional block storage format, but performance decreases due to multiple mapping layers and increased latency
Solution Approach 1:
The patent removes the traditional translation layer from the storage system architecture. Instead of using a Flash Translation Layer (FTL) to map logical key/value addresses to physical block locations, the system directly stores key/value pairs in the flash memory, eliminating the complexity of multiple mapping layers and improving transaction throughput
Solution Approach 2:
The patent segments the storage space into key-value specific regions rather than traditional block structures. Each key/value pair is allocated its own storage region with dedicated metadata, eliminating the need for complex translation mappings and reducing latency
2Reliability
If traditional ECC coding is used on entire data blocks, then error correction is provided, but latency increases due to processing large blocks and reduced correction capability
Solution Approach 1:
The patent divides traditional large data blocks into smaller sub-code blocks for independent ECC processing. Each sub-code block is processed separately by the ECC engine, reducing the time required for error correction while maintaining or improving correction capability through finer-grained error detection and correction
Solution Approach 2:
The patent applies different ECC coding strategies to different portions of data based on their importance and access patterns. Critical data portions receive stronger error correction while less critical portions use lighter coding, optimizing both reliability and processing latency
3Ease of manufacture
If parity bits are uniformly distributed across all data, then simple ECC processing is achieved, but correction capability is reduced for specific data portions
Solution Approach 1:
The patent implements asymmetric parity distribution where different portions of data receive different amounts of parity protection based on their importance. Critical data regions receive higher parity density while less critical regions receive lower density, optimizing correction capability where needed while maintaining processing efficiency
Solution Approach 2:
The patent applies localized quality enhancement by concentrating ECC resources on specific data portions that require higher reliability. This allows the system to maintain overall processing simplicity while providing enhanced correction capability for critical data regions
Data Source
AI summary
Error correction code (ECC) coding for key-value data storage devices. In one embodiment, a controller includes a memory interface configured to interface with a memory; an ECC engine configured to perform ECC coding on data stored in memory; a controller memory including a flash translation layer and a namespace database; and an electronic processor. The electronic processor is configured to receive data to be stored, separate the data into a plurality of sub-code blocks, and allocate parity bits to each sub-code block of the plurality of sub-code blocks.