K-way Systolic Merge Sorter for High-Density Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional merge sort algorithms face challenges when sorting long sequences, as they require significant silicon area, power, and cost, and are inefficient when using serially accessed commercial memory chips, which limits their performance in parallel processing architectures.
Innovation Solution
A K-way systolic merge sorter system that includes a clock signal generator, a systolic array circuit with processing modules and registers, and control circuitry for serially presenting data items, allowing for efficient sorting of long sequences by exchanging data items between registers and processing modules in synchronization with clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional merge sort is implemented with serially accessed memory chips, then the system can use low-cost high-density memory, but the sorting speed is limited due to serial access constraints
Solution Approach 1:
The patent divides the sorting process into multiple independent stages (input stage, processing stages, output stage) that can operate simultaneously. Each processing node handles a portion of the data in parallel, overcoming the serial access limitation while maintaining compatibility with standard memory chips.
Solution Approach 2:
The patent transitions from sequential 2-way merging to parallel K-way merging by adding spatial dimensions to the processing architecture. Multiple processing nodes operate concurrently on different data elements, transforming the time-series serial operation into a spatially parallel operation.
2Productivity
If maximum parallel processing architecture is used with custom hardware accelerators, then sorting speed improves to O(n+log2n) clock cycles, but silicon area, weight, power, and cost increase significantly
Solution Approach 1:
The patent designs processing nodes that can handle multiple data items simultaneously through K-way merging, increasing functional density without proportionally increasing hardware area. Each node performs comparative operations on K inputs to produce one sorted output, achieving higher throughput per unit area.
Solution Approach 2:
The patent changes the merging parameter from traditional 2-way to K-way merging, where K > 2. This parameter change allows more data to be processed in each clock cycle without requiring proportional increases in hardware resources, improving the area-time product efficiency.
3Device complexity
If conventional 2-way merge sort is used, then the algorithm is simple to implement, but the processing time is too long for long sequences
Solution Approach 1:
The patent performs preliminary organization of data into K groups that can be merged simultaneously. By pre-structuring the input data and processing pipeline, the system enables parallel K-way merging operations that reduce overall processing time while maintaining implementation feasibility.
Data Source
AI summary
A sorter system includes a clock continuously generating a series of clock signals, a systolic array circuit, and control circuitry in communication with serial access memory that stores data items of a sequence to be sorted and with the systolic array circuit to supply thereto data items as input and to receive therefrom data items as output. The systolic array circuit includes at least one processing module and K−1 registers, where K is an integer value greater than two. Each processing module has at least one of the registers, each register for storing one data item. The control circuitry serially presents K data items for input to the systolic array circuit in synchronization with the clock signals. On the next clock cycle after the control circuitry presents to the systolic array circuit the last of the K data items, the data item of least value in the given subsequence is output.