L-Shaped Gate Isolation in Stacked CFETs for Independent Control
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Solution Overview
Problem
Existing technologies face challenges in reducing the cell active area footprint and achieving independent control of nFET and pFET transistors in complementary field effect transistors (CFETs) due to the need for separate devices and scaling limitations.
Innovation Solution
A semiconductor structure is developed with a dielectric structure that isolates top and bottom gates of stacked transistors, using an L-shaped middle dielectric portion and plugs to allow separate control of nFET and pFET transistors, enabling them to be stacked while maintaining independent control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If nFET and pFET transistors are stacked in the same gate line, then the cell active area footprint is reduced, but the gates may short together without proper isolation
Solution Approach 1:
The gate line is segmented into multiple independent gate regions (first gate line portion and second gate line portion) that are electrically isolated from each other. This segmentation allows separate control of nFET and pFET transistors while maintaining compact stacking, resolving the contradiction between reduced footprint and gate isolation reliability.
Solution Approach 2:
A dielectric structure is introduced as an intermediary element between the first and second gate line portions. This dielectric structure prevents direct electrical contact between the gates while allowing the transistors to be stacked in close proximity, thereby reducing footprint without compromising gate isolation.
2Adaptability or versatility
If separate devices are used for p-type and n-type wire stacks, then independent control is achieved, but the device complexity and area increase
Solution Approach 1:
Multiple transistor types (nFET and pFET) are merged into a single integrated structure within the same gate line. The gate line contains both first gate line portions for nFET control and second gate line portions for pFET control, enabling independent control of different transistor types while reducing device complexity and eliminating the need for separate devices.
Solution Approach 2:
The gate line structure is designed with multi-functionality to serve dual purposes: it provides independent control signals for both nFET and pFET transistors while maintaining a unified structural framework. This universality reduces device complexity compared to using entirely separate devices for each transistor type.
3Device complexity
If traditional gate-all-around FETs are used, then simple structure is achieved, but scaling is limited due to n-to-p separation bottleneck
Solution Approach 1:
The transistor structure transitions from planar to three-dimensional stacking, with transistors arranged vertically in multiple layers within the gate line. This dimensional change enables continued scaling by utilizing the vertical dimension, overcoming the n-to-p separation bottleneck that limits traditional two-dimensional scaling.
Solution Approach 2:
Multiple transistor structures are nested within each other in a vertical stacking arrangement, with transistors positioned at different height levels within the same gate line footprint. This nesting approach enables high-density integration and continued scaling while maintaining structural simplicity through a unified gate line framework.
Data Source
AI summary
A semiconductor has a gate line with a gate line opening flanked by a pair of source/drains. In the gate line opening are a bottom transistor and a top transistor. The bottom transistor includes a bottom set of nanosheets wrapped by a bottom workfunction material while the top transistor includes a top set of nanosheets wrapped by a top workfunction material. A dielectric structure separates the bottom transistor and the top transistor. The dielectric structure includes a middle dielectric portion (which can be L-shaped), a first plug laterally contacting a first side of the middle dielectric portion and a second plug laterally contacting a second side of the middle dielectric portion.