L-Shaped Floating Gate for Reduced Capacitive Coupling
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Solution Overview
Problem
Conventional flash memory devices face challenges in reducing bit line pitch and forming word line wraparound due to restricted feature dimensions, leading to increased floating gate to floating gate capacitive coupling and reduced device performance.
Innovation Solution
The use of L-shaped and mirrored L-shaped floating gates in flash memory devices allows for more flexible word line wraparound and reduced capacitive coupling, improving device performance by optimizing bit line pitch and capacitive coupling ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional floating gate structures are used, then manufacturing is simpler, but bit line pitch cannot be reduced and capacitive coupling increases
Solution Approach 1:
The floating gate is divided into multiple segments (first floating gate segment and second floating gate segment) separated by a gap. This segmentation breaks the continuous capacitive coupling path between adjacent memory cells, thereby reducing capacitive coupling noise while allowing reduced bit line pitch
Solution Approach 2:
The floating gate structure transitions from a symmetric continuous shape to an asymmetric segmented shape with gaps. This asymmetric segmentation creates electrical isolation between segments, reducing unwanted capacitive coupling while maintaining the memory cell functionality
2Adaptability or versatility
If conventional floating gate structures are used, then device structure is simpler, but word line wraparound is restricted
Solution Approach 1:
The floating gate is segmented into multiple parts that can be independently positioned and configured. This segmentation enables the word line to wrap around the floating gate structure more flexibly, as each segment can be optimized for its specific spatial location, achieving better adaptability without excessive complexity
Solution Approach 2:
The floating gate structure extends into the vertical dimension with segments positioned at different heights and depths. This three-dimensional arrangement allows word lines to wrap around the structure more effectively, providing design flexibility that cannot be achieved with planar two-dimensional structures
3Quantity of substance
If bit line pitch is reduced, then device density increases, but capacitive coupling between floating gates increases
Solution Approach 1:
By segmenting the floating gate into separated sections with gaps between them, the patent reduces the effective capacitive coupling area between adjacent floating gates. This allows bit line pitch to be reduced and device density increased without proportionally increasing capacitive coupling interference
Solution Approach 2:
The gap structure acts as an intermediary element between adjacent floating gate segments. This intermediate region provides electrical isolation and reduces the direct capacitive coupling path, enabling closer spacing of bit lines while maintaining signal integrity
Data Source
AI summary
Various embodiments include a substrate and a memory cell coupled to the substrate. The memory cell may include an L-shaped floating gate, a control gate, an insulation layer coupled between the control gate and the first L-shaped floating gate, and a conductive layer coupled between the substrate and the first L-shape floating gate. Other embodiments including additional apparatus, systems, and methods are disclosed.