L-Shaped Floating Gate NOR Memory Cell Design
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Solution Overview
Problem
As memory cell sizes scale down, maintaining strong capacitive coupling between the floating gate and the source line, low capacitive coupling between the floating gate and the control gate, and high electric charge storage capacity becomes challenging, leading to lower signal-to-noise ratios and higher error rates due to decreased capacitive coupling and charge storage capacity.
Innovation Solution
The implementation of an L-shaped floating gate with a vertical portion strongly capacitively coupled to the source line and a horizontal portion with weak coupling to the control gate, enhancing capacitive coupling and charge storage capacity through increased surface area and focused electric field during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell sizes are scaled down, then device density is improved, but capacitive coupling between floating gate and source line deteriorates
Solution Approach 1:
The floating gate is configured in an L-shape with a vertical portion extending upward from the horizontal portion. This vertical extension increases the surface area of the floating gate that is positioned adjacent to the source line, thereby enhancing capacitive coupling in the vertical dimension without increasing lateral footprint. This dimensional change allows stronger coupling while maintaining scaled-down cell size.
Solution Approach 2:
The L-shaped floating gate creates different coupling characteristics in different regions: the vertical portion provides strong capacitive coupling to the source line, while the horizontal portion provides weak coupling to the control gate. This spatial differentiation of coupling strength allows simultaneous optimization of erase efficiency (requiring strong source line coupling) and programming efficiency (requiring weak control gate coupling).
2Productivity
If floating gate size is scaled down, then device density is improved, but charge storage capacity deteriorates
Solution Approach 1:
The vertical portion of the L-shaped floating gate extends in the vertical dimension, increasing the total surface area available for charge storage without increasing the lateral footprint. This allows the floating gate to maintain or increase charge storage capacity while the memory cell size is scaled down, thereby improving device density without sacrificing charge storage capability.
Solution Approach 2:
Different portions of the L-shaped floating gate serve different functions: the vertical portion primarily provides charge storage capacity and strong coupling to the source line, while the horizontal portion provides weak coupling to the control gate. This functional differentiation allows the floating gate to simultaneously achieve high charge storage capacity and optimized coupling characteristics despite reduced overall size.
3Productivity
If floating gate size is scaled down, then device density is improved, but signal-to-noise ratio deteriorates
Solution Approach 1:
The vertical extension of the floating gate increases the surface area adjacent to the source line, enhancing capacitive coupling and thereby improving the signal strength during erase operations. This stronger signal improves the signal-to-noise ratio even as the overall cell size is reduced for higher device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves erase efficiency, programming efficiency, and signal-to-noise ratios by maintaining strong capacitive coupling with the source line and low coupling with the control gate, reducing error rates and increasing charge storage capacity.
Implementation Method 1
The second floating gate portion extends vertically from the first floating gate portion and away from the substrate, and is strongly capacitively coupled to a source line that extends vertically from the source region
Implementation Method 2
an electrically conductive L-shaped floating gate, including a first, horizontal first portion separated from a second channel sub-region by a floating gate insulation region
Data Source
AI summary
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a second substrate region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the second substrate region, an electrically conductive control gate insulated from and disposed over a first channel portion of the channel region, an electrically conductive floating gate insulated from and disposed over a second channel portion of the channel region, an electrically conductive source line electrically connected to the second substrate region, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.