L-Shaped Floating Gate Non-Volatile Memory for Low Voltage Operation
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Solution Overview
Problem
Conventional EEPROMs face challenges in reducing working voltage and enhancing operational speed due to decreased gate-coupling ratio (GCR) as linewidths decrease, particularly in portable electronic products requiring low energy consumption.
Innovation Solution
The design incorporates an L-shaped floating gate with a circular arc curve sidewall, increasing the capacity area between the floating gate and control gate, and a self-aligned manufacturing method to enhance GCR, reduce working voltage, and accelerate operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the linewidth of the memory device is reduced to decrease the area occupied by each memory cell, then the area efficiency is improved, but the gate-coupling ratio (GCR) between the floating gate and the control gate is decreased
Solution Approach 1:
The floating gate is designed with an L-shaped cross-section that extends in multiple dimensions. The first conductive layer forms a structure that protrudes from the substrate surface and extends laterally, increasing the overlapping area with the control gate in three-dimensional space rather than being limited to a planar configuration.
Solution Approach 2:
The L-shaped floating gate structure is formed by nesting conductive layers within dielectric layers. The first conductive layer is embedded in the first dielectric layer, and the second conductive layer is formed on the sidewall of the first conductive layer, creating a nested configuration that maximizes space utilization and coupling area.
2Use of energy by stationary object
If the gate-coupling ratio (GCR) is increased to reduce the working voltage, then the energy consumption is reduced, but the manufacturing complexity increases
Solution Approach 1:
The first conductive layer is formed with a protruding structure before the second conductive layer is deposited. This preliminary formation of the L-shaped structure ensures that the floating gate already has the optimized geometry for high GCR before the control gate is formed, simplifying subsequent manufacturing steps.
Solution Approach 2:
The self-aligned manufacturing process utilizes the first conductive layer as a mask for forming the second conductive layer. The second conductive layer is formed on the sidewall of the first conductive layer through a self-aligned process, eliminating the need for additional alignment steps and reducing manufacturing complexity.
Data Source
AI summary
A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.