L-Shaped Bottom Semiconductor Structure for Sub-80 nm Patterning
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Solution Overview
Problem
As semiconductor devices continue to shrink, achieving higher device density becomes challenging due to limitations in patterning techniques, particularly for sub-80 nm pitch, where conventional sidewall imaging transfer (SIT) methods struggle to efficiently form dense patterns while maintaining structural integrity and alignment.
Innovation Solution
The method involves forming 'L' shaped vertical transistors by aligning the vertical side of a fin with the source/drain semiconductor structure, using a combination of sidewall imaging transfer, selective etching, and deposition techniques to create spacers and source/drain structures that extend perpendicularly, allowing for increased packing density and improved structural alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional sidewall imaging transfer (SIT) methods are used for sub-80 nm pitch patterning, then pattern density can be doubled, but structural integrity and alignment precision deteriorate
Solution Approach 1:
The patent divides the source/drain structure formation into multiple stages: first forming mandrels with initial spacers, then selectively removing portions to create the L-shaped configuration. This segmentation allows each step to be optimized independently, maintaining alignment precision while achieving high pattern density.
Solution Approach 2:
The L-shaped source/drain structure creates different geometries in different regions: the vertical portion aligns with the channel for precise positioning, while the horizontal portion extends to increase effective width. This local variation in geometry enables simultaneous achievement of alignment precision and pattern density.
2Quantity of substance
If device real estate is continuously scaled down to increase device density, then transistor count increases, but patterning capability and structural integrity worsen
Solution Approach 1:
The L-shaped source/drain structure is formed by nesting geometric operations: the vertical channel portion is nested within the overall device footprint, while the horizontal source/drain portion extends outward. This nested geometry maximizes space utilization while maintaining structural soundness at scaled dimensions.
Solution Approach 2:
The patent transitions from conventional planar patterning to three-dimensional L-shaped structures. By utilizing vertical extension in addition to horizontal spacing, the design achieves higher device density without compromising the structural integrity of individual components.
3Ease of manufacture
If blanket deposition of spacer material is performed for SIT process, then spacer formation is simplified, but material waste and process complexity increase
Solution Approach 1:
Instead of using blanket deposition followed by extensive removal, the patent extracts only the necessary spacer material portions through selective etching. The L-shaped geometry is achieved by removing specific regions rather than depositing excess material everywhere, thereby reducing material waste while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances packing density and structural alignment, enabling the formation of densely packed vertical transistors with increased transistor density and improved manufacturing efficiency in semiconductor fabrication processes.
Implementation Method 1
Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions
Implementation Method 2
spacers are then made out of the blanket layer of spacer making material through a directional etching process
Data Source
AI summary
A method of forming a semiconductor structure is provided. The method including forming a first vertical channel on a first layer of source/drain material that is perpendicular relative to the first vertical channel, and forming a first source/drain semiconductor structure by removing one or more portions of the first layer of source/drain material such that i) the first source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel and ii) a width of the source/drain is greater than a width of the first vertical channel, wherein the first source/drain semiconductor structure extends perpendicularly from its vertical side farther than the first vertical channel extends perpendicularly from its vertical side.