L-Shaped Bottom Source/Drain Regions for High-Density VT FinFET SRAM
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Solution Overview
Problem
As device dimensions decrease, traditional FET structures face scaling issues, making it difficult to form smaller components and electrical contacts, which affects memory cell density and increases leakage, necessitating a solution to reduce the footprint of bottom source/drain regions in SRAM cells.
Innovation Solution
The implementation of L-shaped bottom source/drain regions with self-aligned and patterned portions, allowing for nesting of adjacent transistor regions, reduces the memory cell area and increases integration density without reducing fin and gate structure dimensions, using vertical transport fin field effect transistors (VT FinFETs) with p-type and n-type dopants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device dimensions are decreased to increase memory density, then memory cell footprint is reduced, but manufacturing difficulty increases and leakage increases
Solution Approach 1:
The patent applies nesting by placing one bottom source/drain region inside another bottom source/drain region. Specifically, a first bottom source/drain region is formed, then a second bottom source/drain region is formed inside it, creating a nested configuration that reduces the overall footprint of the memory cell while maintaining manufacturability through self-aligned processes.
Solution Approach 2:
The patent transitions from traditional planar bottom source/drain regions to vertically stacked three-dimensional structures. By forming bottom source/drain regions at different vertical levels and nesting them, the design utilizes the vertical dimension to reduce lateral footprint while maintaining electrical functionality.
2Area of moving object
If device dimensions are decreased to increase memory density, then memory cell footprint is reduced, but leakage increases
Solution Approach 1:
The nested configuration of bottom source/drain regions creates overlapping doped regions that form potential wells, which help confine carriers and reduce off-state leakage current while maintaining compact dimensions.
Solution Approach 2:
The patent applies local quality by creating regions with different doping types (n-type and p-type) in specific locations within the nested structure. This localized doping strategy creates potential barriers at critical interfaces to suppress leakage while maintaining low resistance where needed.
3Ease of manufacture
If traditional FET structures are used, then manufacturing is easier, but memory cell density is lower
Solution Approach 1:
The patent segments the bottom source/drain structure into multiple distinct regions (first bottom source/drain region, second bottom source/drain region) that can be formed through separate but self-aligned manufacturing steps. This segmentation allows for optimized doping and positioning while maintaining compatibility with existing fabrication processes.
Solution Approach 2:
The patent uses preliminary action through self-aligned formation where the first bottom source/drain region is formed first, and then the second bottom source/drain region is formed in a subsequent step that is automatically aligned to the first region. This preliminary positioning simplifies the overall manufacturing process by eliminating the need for additional alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the formation of smaller VT FinFET SRAMs with higher memory density and reduced leakage, maintaining the positive aspects of traditional FET structures while overcoming scaling challenges.
Implementation Method 1
a first L-shaped bottom source/drain including a p-type dopant, and a vertical fin on the first L-shaped bottom source/drain... and a first adjoining bottom source/drain region including an n-type dopant
Data Source
AI summary
In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.