L-Shaped Spacer for Vertical Transistor Gate Length Control

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Solution Overview

Problem

Conventional fabrication processes for vertical transistors result in significant variations in gate length, affecting device properties and performance.

Innovation Solution

The use of an L-shaped spacer is introduced to protect the gate region from subsequent etch and polish steps, ensuring precise control and repeatability in gate length by forming spacers with an L-shaped cross-section above the vertical channel fin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional fabrication processes are used for vertical transistors, then device scaling and transistor density are improved, but gate length variation increases

Engineering Contradiction:
Improvetransistor densityVSAvoidgate length control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The spacer structure is formed in advance before the gate material deposition. The L-shaped spacer with its specific geometry (first portion extending from sidewall, second portion extending from top surface) is created as a preliminary structure that defines the eventual gate length boundaries. This preliminary action establishes precise dimensional constraints that guide subsequent gate formation processes, ensuring consistent gate length across devices while maintaining high transistor density.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If etch and polish steps are applied to the gate region, then device performance is improved, but gate length precision deteriorates

Engineering Contradiction:
Improvedevice performanceVSAvoidgate length precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The L-shaped spacer structure is designed to preemptively counteract the harmful effects of etch and polish steps on gate length precision. The spacer's geometry (with portions extending from both sidewall and top surface) creates a protective framework that limits material removal during etching and polishing operations. This preliminary anti-action ensures that beneficial etch and polish steps improve device performance without compromising gate length precision.

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If the gate stack extends beyond the channel fin base portion, then gate coverage is improved, but gate length control worsens

Engineering Contradiction:
Improvegate coverageVSAvoidgate length control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The spacer structure implements local quality by having different portions serve different functions: the first portion (extending from sidewall) provides lateral definition for gate length control, while the second portion (extending from top surface) ensures adequate gate coverage. This spatial differentiation of functions within the spacer structure allows simultaneous achievement of precise gate length control and sufficient gate coverage without compromise.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10297689B2Precise control of vertical transistor gate length
Publication Date: 2019.05.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10297689B2 patent drawing
  • US10297689B2 patent drawing
  • US10297689B2 patent drawing

AI summary

A transistor includes a vertical channel fin on a bottom source/drain region. The vertical channel fin includes a base portion and an upper portion. The base portion has a width greater than a width of the upper portion and a top surface height greater than a top surface height of the bottom source/drain region. A gate stack formed on sidewalls of the vertical channel fin. Spacers are formed above the gate stack, one above each sidewall of the vertical channel fin. A top source/drain region is formed between the spacers.