L1 Cache Line Aligned Bitmap Chunks for Multicore Allocation

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Solution Overview

Problem

Hybrid storage devices face challenges in optimally allocating different types of data to variously performing components, leading to performance issues due to metadata consistency and cache line invalidations, which degrade latency and throughput during concurrent access by multiple CPU cores.

Innovation Solution

The solution involves dividing the fast tier into zones for metadata, fast data, and a spillover zone, allowing metadata and fast data to be mixed in the spillover zone, and using a policy-based allocator to dynamically allocate space across these zones, while dividing cluster allocation bitmaps into L1 cache line sized and aligned chunks to mitigate cache line invalidations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If locks are used to maintain metadata consistency during concurrent access, then data integrity is improved, but latency and throughput are degraded due to stalls and context switches

Engineering Contradiction:
Improvemetadata consistencyVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the cluster allocation bitmap into multiple chunks, where each chunk can be independently accessed by different threads. This segmentation allows concurrent access to different portions of the bitmap without requiring global locks, thereby maintaining metadata consistency while improving throughput by eliminating stalls and context switches associated with lock contention.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple CPU cores concurrently access the same metadata, then productivity is improved, but cache line invalidations occur causing stalls and degrading performance

Engineering Contradiction:
Improveconcurrent access efficiencyVSAvoidcache stall time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By dividing the bitmap into multiple cache-line-sized chunks and allowing different cores to access different chunks simultaneously, the patent eliminates cache line invalidations between cores. Each core works on its own chunk without interfering with others, maintaining high concurrent access efficiency while avoiding cache stalls.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent assigns specific chunks of the bitmap to specific CPU cores or thread groups, creating localized access patterns. This ensures that each core operates on dedicated data segments, improving concurrent access efficiency while preventing cache line invalidations that would otherwise occur when multiple cores access the same metadata.

Inventive Principle:
Principle #3Local quality

3Speed

If the fast tier is dedicated to metadata storage, then metadata access performance is improved, but utilization of the fast tier is reduced

Engineering Contradiction:
Improvemetadata access speedVSAvoidfast tier utilization
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent enables the fast tier to serve multiple purposes: it can store metadata when needed while also being available for general data storage. By allowing flexible allocation between metadata and data across the fast tier, the system maintains high metadata access speed while maximizing fast tier utilization through dynamic resource sharing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3752924B1Central processing unit cache friendly multithreaded allocation
Publication Date: 2023.09.06 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3752924B1 patent drawingFigure 1
  • EP3752924B1 patent drawingFigure 2
  • EP3752924B1 patent drawingFigure 3

AI summary

In order to better utilize storage devices, many filesystems allow concurrent access to a cluster allocation bitmap. A cluster allocation bitmap determines which clusters in a band of storage remain unallocated. However, concurrent access to a cluster allocation bitmap can cause CPU stalls as copies of the cluster allocation bitmap in a CPU's level 1 (L1) cache are invalidated by another CPU allocating from the same bitmap. In one embodiment, cluster allocation bitmaps are divided into L1 cache line sized and aligned chunks. Each core of a multicore CPU is directed at random to allocate space out of a chunk. Because the chunks are L1 cache line aligned, the odds of the same portion of the cluster allocation bitmap being loaded into multiple L1 caches by multiple CPU cores is reduced, reducing the odds of an L1 cache invalidation.