L1 Data Cache Hazard Control for DMA Snoop Write Conflicts
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Solution Overview
Problem
In digital signal processor systems with a two-level memory subsystem, cache coherency issues arise due to asynchronous L1D cache misses during DMA writes, where L2 memory may incorrectly assume data is cached in L1D, leading to snoop writes before the data is actually available, causing performance hazards.
Innovation Solution
Implementing a mechanism to stall DMA writes until pending reads are completed, using a monitor memory to store read addresses and a FIFO stack for DMA accesses, with a comparator ensuring no conflicts exist before allowing DMA writes to proceed, thereby maintaining cache coherency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If L2 controller sends snoop writes to L1D during DMA writes, then DMA data is forced to L1D cache, but cache coherency issues occur when L1D cache miss data has not landed yet
Solution Approach 1:
The patent implements a hazard detection mechanism that checks whether L1D cache miss data has landed before allowing snoop writes from L2 to proceed. This preliminary check prevents coherency hazards by ensuring data availability before write operations, resolving the contradiction between maintaining coherency and preserving DMA write performance
Solution Approach 2:
The patent introduces an intermediary hazard detection mechanism between the L2 controller and L1D cache that mediates the timing conflict. This intermediary checks the status of cache miss data and controls when snoop writes can proceed, preventing coherency issues without stalling DMA writes unnecessarily
2Reliability
If DMA writes are stalled to prevent coherency issues, then cache coherency is maintained, but performance is reduced due to unnecessary stalls
Solution Approach 1:
The patent implements a feedback mechanism where the hazard detection unit continuously monitors the status of L1D cache miss data and provides real-time feedback to control snoop write operations. This feedback system ensures DMA writes are stalled only when necessary (when data has not landed), maintaining coherency while minimizing performance loss
Solution Approach 2:
The patent makes the DMA write stalling dynamic rather than static. The hazard detection mechanism dynamically determines whether to stall based on the actual status of cache miss data, allowing DMA writes to proceed without stalls when data is available and imposing stalls only when coherency would be compromised
Data Source
AI summary
A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.