L1 Cache Access Using Effective Addresses to Bypass Translation
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Solution Overview
Problem
Modern processors face increased access time and overhead due to address translation in accessing Level 1 caches, especially when multiple cores perform address translation simultaneously.
Innovation Solution
The method involves executing access instructions with untranslated effective addresses to determine if data is present in the Level 1 cache, bypassing address translation to reduce processing overhead and improve speed by directly accessing the Level 1 cache if data is found, or using the Level 2 cache if not.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address translation is performed before L1 cache access, then address translation enables access to larger address space, but access time to L1 cache increases
Solution Approach 1:
The patent segments the cache access process into two distinct paths: L1 cache access using effective addresses (bypassing address translation) and L2 cache access using real addresses (with address translation). This segmentation allows the frequently accessed L1 cache to operate at higher speed while address translation is performed asynchronously for L2 cache operations.
Solution Approach 2:
The patent introduces a translation lookaside buffer (TLB) as an intermediary structure that caches address translation mappings. The TLB stores recent effective-to-real address translations, allowing the system to retrieve translations quickly without blocking L1 cache access, thus resolving the speed conflict between address translation and cache access.
2Productivity
If address translation circuitry is provided for each core, then each core can independently perform address translation, but overhead from providing and performing address translation increases
Solution Approach 1:
The patent merges the address translation function into a shared resource that is accessed asynchronously by multiple cores. Instead of each core having dedicated address translation circuitry, the translation operations are consolidated and performed in parallel using available translation resources, reducing overall power consumption while maintaining productivity.
Solution Approach 2:
The patent performs address translation in advance and stores the mappings in the translation lookaside buffer (TLB). By pre-translating addresses and caching the results, the system eliminates the need for repeated address translation operations, thereby reducing power consumption for address translation while maintaining high productivity during cache accesses.
3Reliability
If address translation is performed for every cache access, then correct real addresses are obtained, but processing overhead increases
Solution Approach 1:
The patent applies partial address translation by performing translation only when necessary (for L2 cache misses or when effective addresses are not in the TLB). For L1 cache accesses, the system uses effective addresses directly without translation, reducing processing overhead while maintaining reliability through selective translation based on cache hit/miss outcomes.
Solution Approach 2:
The patent performs address translation in advance and stores mappings in the translation lookaside buffer (TLB). This preliminary translation action allows subsequent cache accesses to use pre-translated addresses, eliminating the need for repeated translation operations and reducing processing overhead while ensuring address translation accuracy is maintained.
Data Source
AI summary
A method and apparatus for accessing a processor cache. The method includes executing an access instruction in a processor core of the processor. The access instruction provides an untranslated effective address of data to be accessed by the access instruction. The method also includes determining whether a level one cache for the processor core includes the data corresponding to the effective address of the access instruction. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address. If the level one cache includes the data corresponding to the effective address, the data for the access instruction is provided from the level one cache.