L1 Cache Ownership Request Reduces L2 Transaction Pressure
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Solution Overview
Problem
Conventional chip multiprocessors (CMPs) face increased L2 cache miss rates and latency due to competition for storage space in the shared L2 cache, where private data from one processor core displaces more useful data, leading to inefficient use of on-chip resources and increased transaction pressure on the crossbar and shared L2 cache.
Innovation Solution
An enhanced CMP method allows an L1 cache to request ownership of a data line from a shared L2 cache, determining whether reuse is likely and granting or denying ownership based on sharing, thereby reducing the need for data to pass through the shared L2 cache and minimizing competition for storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If private data from one processor core is stored in the shared L2 cache, then data storage capacity is increased, but L2 cache miss rate increases and latency increases due to displacement of more useful data
Solution Approach 1:
The patent segments the shared L2 cache into private regions for each processor core and shared regions for common data. Each core's private data is stored in its dedicated private region, preventing displacement of other cores' useful data. This segmentation resolves the contradiction by maintaining storage capacity while eliminating cache misses caused by private data displacement.
Solution Approach 2:
The patent extracts private data from the shared L2 cache namespace and places it in private cache regions within each processor core. By taking out private data from the shared space, the system prevents private data from displacing useful shared data, thereby reducing L2 cache miss rates while maintaining adequate storage capacity through the combined private and shared regions.
2Quantity of substance
If private data from one processor core is stored in the shared L2 cache, then data storage capacity is increased, but latency increases due to competition for storage space
Solution Approach 1:
The patent segments the shared L2 cache into private regions for each processor core and shared regions for common data. Each core's private data is stored in its dedicated private region, eliminating competition for storage space and reducing access latency. This segmentation maintains storage capacity while preventing latency increases caused by data displacement and cache conflicts.
3Reliability
If all stores go through the shared L2 cache, then memory coherence is maintained, but transaction pressure on the crossbar and shared L2 cache increases
Solution Approach 1:
The patent segments memory access paths into private store paths for each processor core and shared paths for common data. Private stores are directed to the owning core's private cache region without traversing the shared L2 cache or crossbar, thereby maintaining memory coherence through ownership tracking while dramatically reducing transaction pressure on shared resources.
Solution Approach 2:
The patent extracts private store transactions from the shared L2 cache path and routes them directly to the owning core's private cache region. By taking out private stores from the shared path, the system maintains memory coherence through ownership tracking while eliminating unnecessary transactions through the crossbar and shared L2 cache, thus reducing transaction pressure.
4Reliability
If L1 cache requests ownership of data line from shared L2 cache, then competition for storage space is reduced, but additional ownership management overhead is introduced
Solution Approach 1:
The patent implements self-service ownership management where each L1 cache autonomously requests and manages ownership of data lines in its private cache region without requiring L2 cache intervention. The L1 cache tracks its own ownership state and handles coherence independently, reducing competition for storage space while minimizing ownership management overhead through decentralized, self-managed coherence protocols.
Data Source
AI summary
In accordance with one embodiment, an enhanced chip multiprocessor permits an L1 cache to request ownership of a data line from a shared L2 cache. A determination is made whether to deny or grant the request for ownership based on the sharing of the data line. In one embodiment, the sharing of the data line is determined from an enhanced L2 cache directory entry associated with the data line. If ownership of the data line is granted, the current data line is passed from the shared L2 to the requesting L1 cache and an associated enhanced L1 cache directory entry and the enhanced L2 cache directory entry are updated to reflect the L1 cache ownership of the data line. Consequently, updates of the data line by the L1 cache do not go through the shared L2 cache, thus reducing transaction pressure on the shared L2 cache.