L1 Cache Reorder Buffer Elimination

Solution Overview

Problem

In digital signal processors with L1 and L2 cache memories, there is no guarantee that data requested by the CPU will be returned in the correct order, leading to the need for a reorder buffer, which increases processor size and operational frequency, and area requirements.

Innovation Solution

Reusing the existing L1 cache memory to fulfill the function of the reorder buffer, eliminating the need for a dedicated reorder buffer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated reorder buffer is used to guarantee correct data return order, then reliability is improved, but device complexity and area increase

Engineering Contradiction:

Improvedata return order guaranteeVSAvoidreorder buffer size

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The L1 cache is designed to perform multiple functions: it serves as both the primary cache for storing frequently accessed data and as a reorder buffer for managing out-of-order data returns from L2 cache. By making the L1 cache universal, the patent eliminates the need for a separate dedicated reorder buffer, thereby reducing device complexity and area while maintaining the reliability of correct data return order through software-managed reordering

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a dedicated reorder buffer is used to guarantee correct data return order, then reliability is improved, but processor area increases

Engineering Contradiction:

Improvedata return order guaranteeVSAvoidcore area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The L1 cache is designed to perform multiple functions: it serves as both the primary cache for storing frequently accessed data and as a reorder buffer for managing out-of-order data returns from L2 cache. By making the L1 cache universal, the patent eliminates the need for a separate dedicated reorder buffer, thereby reducing device complexity and area while maintaining the reliability of correct data return order through software-managed reordering

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If a large reorder buffer is used to handle increased outstanding memory requests, then productivity is improved, but device complexity and area increase

Engineering Contradiction:

Improveoutstanding memory requests capacityVSAvoidreorder buffer size

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system uses software (firmware or operating system) to manage the reordering of data returns from L2 cache to CPU, rather than relying on hardware buffer expansion. This self-service approach allows the L1 cache to handle multiple functions including the reordering task, enabling the system to support increased outstanding memory requests without proportionally increasing hardware complexity or area

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS9652392B2Using L1 cache as re-order buffer

Publication Date: 2017.05.16 TEXAS INSTRUMENTS INC

AI summary

A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the L2 cache may be returned out of order, the L1 cache uses it's cache memory to buffer the out of order data and provides the data to the requesting processor in the correct order from the buffer.