L1 Cache Sharing via Neighbor Access Directory
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Solution Overview
Problem
Modern computing systems face challenges in balancing cache size and latency, as larger caches improve hit rates but increase latency and are limited by space constraints, especially in multi-processor systems where data is shared.
Innovation Solution
Implementing a method to share Level 1 (L1) cache memories between processors, allowing one processor to access data from a neighboring processor's L1 cache if it is not found in its own cache, thereby effectively increasing cache size without physical expansion, and using arbitration logic to manage requests and minimize pipeline disruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache size is increased to store more data, then cache hit rate is improved, but latency increases
Solution Approach 1:
The patent merges the L1 caches of multiple processors into a shared cache structure. Each processor can access data from any processor's L1 cache, effectively combining multiple small caches into one large distributed cache. This resolves the contradiction by increasing the total cache capacity (improving hit rate) without requiring each individual processor to have a larger physical cache, thereby avoiding the latency penalty associated with larger single-processor caches.
Solution Approach 2:
The patent introduces a new dimension to cache organization by enabling cross-processor cache access. Instead of each processor being limited to its own local L1 cache, the system extends the cache dimension across multiple processors through shared access mechanisms and directory structures that track cache line locations across different processors.
2Reliability
If cache size is increased to store more data, then cache hit rate is improved, but chip space is consumed
Solution Approach 1:
The patent combines multiple processors' L1 caches into a shared resource. Rather than each processor allocating its own large cache, the system merges them so that all processors share the same physical cache memory space across the chip. This increases the effective cache size for each processor (improving hit rate) without requiring additional physical cache space on the chip, as the same physical cache serves multiple processors simultaneously.
Solution Approach 2:
The patent makes the L1 cache structure universal by enabling any processor to access data from any other processor's L1 cache. The cache system serves multiple functions: it acts as local cache for each processor while simultaneously serving as a shared cache resource for all processors, thereby increasing cache capacity without proportionally increasing physical footprint.
3Quantity of substance
If L1 cache sharing is implemented between processors, then effective cache size is doubled, but additional hardware is required
Solution Approach 1:
The patent introduces a directory structure as an intermediary mechanism that tracks which processors have cached which data. This directory acts as a mediator that enables processors to efficiently determine whether data is available in other processors' L1 caches before initiating access. The directory manages the complexity of multi-processor cache sharing, allowing effective cache size to double while keeping the additional hardware requirements manageable through a structured tracking approach.
Data Source
AI summary
Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip.