L1 Cache Tag Unit Segmentation for Simultaneous Access
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Solution Overview
Problem
In processor architectures with a super-scalar architecture, the data unit of the L1 cache implemented as RAM restricts simultaneous access operations, leading to reduced processing efficiency due to the need to adjust operation timing between consecutive store instructions, which affects overall performance.
Innovation Solution
A cache control apparatus with a data unit storing data index-specifically and a tag unit storing tags and error flags, allowing simultaneous read and write access to the tag unit, enabling process scheduling that performs read and other accesses to the tag unit simultaneously without requiring additional data unit access for error checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data unit of the L1 cache is implemented as RAM to enable error checking, then data reliability is improved, but simultaneous access operations in multiple pipelines are restricted, reducing processing efficiency
Solution Approach 1:
The L1 cache is segmented into a tag unit and a data unit. The tag unit stores tag information and error status flags, while the data unit stores actual data. This segmentation allows the tag unit to be accessed for error checking without requiring access to the data unit, enabling simultaneous operations in multiple pipelines.
Solution Approach 2:
The tag unit acts as an intermediary between the control unit and the data unit. By storing error status flags in the tag unit, the system can determine data integrity without accessing the data unit itself, allowing multiple pipelines to operate simultaneously without conflicting for data unit access.
2Measurement precision
If error checking is performed by reading data from the data unit and calculating error correction codes, then error detection accuracy is improved, but access timing must be adjusted to avoid collision with write operations, reducing pipeline performance
Solution Approach 1:
Error status flags are pre-calculated and stored in the tag unit when data is written to the data unit. This preliminary action eliminates the need to read data from the data unit for error checking, as the error status is already available in the tag unit, allowing simultaneous tag unit accesses in multiple pipelines without timing adjustments.
3Reliability
If timing adjustment is performed between consecutive store instructions to avoid collision, then data integrity is maintained, but processing speed decreases due to staggered pipeline operations
Solution Approach 1:
The error checking function is extracted from the data unit access path and placed in the tag unit. By storing error status flags separately in the tag unit, the system can perform error checking through tag unit reads without requiring timing adjustments relative to data unit write operations, enabling multiple pipelines to operate at full speed simultaneously.
Data Source
AI summary
A cache control apparatus includes a data unit configured to store data on an index-specific basis, a tag unit configured to store, on the index-specific basis, a tag and a flag indicating whether the data has an uncorrectable error, and a control unit configured to refer to the flag, upon detecting a tag hit by performing a read access to the tag unit, to determine whether an uncorrectable error exists in the data corresponding to the tag hit, wherein the control unit performs process scheduling such that the read access to the tag unit and another access to the tag unit are performed simultaneously.