L1 Cacheability Bit Copying for Multilevel Cache Write Merging
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Solution Overview
Problem
In prior art devices, memory attribute registers are not visible in the level one data cache controller, preventing performance optimizations such as merge writes for external addresses based on cacheability and optimizing cache state machines, and requiring the level one data cache controller to generate and send victims for read accesses to non-cacheable external addresses.
Innovation Solution
The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register, allowing it to optimize memory system performance by merging writes, optimizing cache state machines, and avoiding unnecessary victim generation for non-cacheable read accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory attribute registers are not visible in the level one data cache controller, then the device complexity is reduced, but the productivity is degraded due to inability to perform merge writes and optimize cache operations
Solution Approach 1:
The patent divides the memory controller functionality into two segments: the level two memory controller maintains the master copy of memory attribute registers, while the level one memory controller maintains a local copy specifically for optimization purposes. This segmentation allows the level one controller to access cacheability information without requiring full visibility of all memory attribute registers, thus improving performance while controlling complexity.
Solution Approach 2:
The level one memory controller creates a local copy of the cacheability bits from the memory attribute registers. This copying mechanism provides the necessary information for performance optimizations (merge writes, state machine optimization, victim generation suppression) without requiring the level one controller to have direct visibility or access to the full set of memory attribute registers, resolving the contradiction between performance and complexity.
2Loss of time
If the level one data cache controller has full visibility of memory attribute registers, then the measurement precision of cacheability information is improved, but the loss of time is reduced due to unnecessary victim generation for non-cacheable addresses
Solution Approach 1:
The level one memory controller proactively maintains a local copy of cacheability bits before actual memory access operations occur. This preliminary action ensures that when read accesses occur, the controller already has the necessary cacheability information to determine whether to generate victims, eliminating delays and unnecessary victim generation while avoiding the complexity of real-time register visibility.
Solution Approach 2:
The local copy of cacheability bits acts as an intermediary between the memory attribute registers and the level one cache controller's decision-making process. This intermediary provides the necessary information for timely decisions about victim generation without requiring direct visibility of the full memory attribute register set, thus reducing time loss while controlling complexity.
3Productivity
If the level one memory controller maintains local copy of cacheability bits, then the productivity is improved through merge writes and optimized state machines, but the device complexity increases due to additional storage and update mechanisms
Solution Approach 1:
The level one memory controller implements local quality by maintaining cacheability information specifically tailored to its operational needs rather than having full visibility of all memory attribute registers. This localized approach provides just enough information (cacheability bits) to enable performance optimizations like merge writes and state machine improvements without the overhead of complete register visibility, thus improving productivity while limiting complexity increase.
Solution Approach 2:
The local copy of cacheability bits serves multiple functions: it enables merge writes for external addresses, optimizes cache state machines through early knowledge of cacheability, and prevents unnecessary victim generation for non-cacheable read accesses. This multi-functionality justifies the additional complexity by providing comprehensive performance improvements across multiple operational areas simultaneously.
Data Source
AI summary
The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.