L1 Program Memory Leakage Reduction via Sleep Mode Voltage Control
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Solution Overview
Problem
As integrated circuits (ICs) become larger and more complex, they consume increasing amounts of power due to switching frequency and DC conditions like leakage in transistors, necessitating effective power reduction methods to manage heating and costs, particularly in DSP ICs with large memory arrays.
Innovation Solution
Implementing a sleep mode operation in L1 program memory by monitoring idle conditions and adjusting voltage levels using NMOSFETs to minimize leakage power, with an arbiter determining when and how long to maintain the sleep mode to balance power savings and switching costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If voltage is reduced to minimize leakage power, then power consumption decreases, but switching speed and system performance may deteriorate
Solution Approach 1:
The patent applies dynamics by making the voltage supply to memory arrays adjustable and time-variable. The memory arrays transition between full voltage (active mode) and reduced voltage (sleep mode) based on real-time access patterns. This dynamic voltage adjustment allows the system to minimize leakage power during idle periods while maintaining full performance when access is needed, resolving the contradiction between power savings and switching speed.
Solution Approach 2:
The patent changes the voltage parameter of the memory arrays based on operational state. By monitoring access patterns and adjusting the voltage level accordingly (full voltage for active, reduced voltage for sleep), the system optimizes the balance between leakage power consumption and switching performance. This parameter change approach enables the memory to adapt its electrical characteristics to current operational requirements.
2Loss of energy
If sleep mode is activated frequently to save power, then leakage power decreases, but switching power increases due to frequent transitions
Solution Approach 1:
The patent implements feedback by monitoring memory access patterns and using this information to control sleep mode activation. The system tracks whether memory arrays are being accessed and adjusts the voltage state accordingly. This feedback mechanism prevents premature or unnecessary transitions to sleep mode, ensuring that sleep mode is only activated when it will result in net power savings, thereby balancing leakage power reduction against switching power consumption.
Solution Approach 2:
The patent applies preliminary action by proactively transitioning memory arrays to sleep mode when access patterns indicate they will not be needed for a sufficient duration. The arbiter monitors access requests and anticipates idle periods, allowing the system to enter sleep mode before leakage would accumulate significantly, while avoiding transitions that would incur excessive switching power overhead.
3Loss of energy
If voltage is reduced in memory arrays, then power consumption decreases, but current leakage control becomes more challenging
Solution Approach 1:
The patent applies segmentation by dividing the memory system into independently controllable segments (memory arrays with associated decode circuits). Each segment can be independently transitioned to sleep mode or kept active based on local access patterns. This segmentation allows for granular voltage control, reducing overall power consumption while managing leakage control complexity through modular, independent control of each memory segment rather than requiring system-wide voltage management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage power consumption while maintaining system performance and transparency to end users, optimizing power management in complex ICs like DSPs by minimizing heating and packaging costs.
Implementation Method 1
adjusting voltage levels using NMOSFETs to minimize leakage power
Data Source
AI summary
An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling a sleep mode in the L1 program memory. The sleep mode determines when the L1 program memory will not be accessed for a period of time. When it is determined that the L1 program memory will not be accessed for a period of time, the voltage applied to the memory array is reduced. When it is determined that the L1 program memory will be accessed, the voltage applied to the memory array is increased.