L1 TLB Prefetching from STLB for Faster Address Translation

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Solution Overview

Problem

Current processors face inefficiencies in managing cache and translation lookaside buffer (TLB) subsystems, particularly in handling infrequently accessed cache lines and virtual-to-physical address translations, leading to suboptimal performance.

Innovation Solution

Implementing an apparatus and method for prefetching from a second level TLB to a first level TLB, optimizing the handling of cache lines and TLB subsystems to improve access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If cache lines are evicted from L1 cache to L2 cache, then memory hierarchy efficiency is improved, but access latency increases

Engineering Contradiction:
Improvememory hierarchy efficiencyVSAvoidaccess latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by prefetching TLB entries from the second level TLB to the first level TLB before they are actually needed. This is achieved by monitoring TLB refill patterns and proactively loading anticipated TLB entries into the faster first level TLB, thereby reducing future access latency without compromising memory hierarchy efficiency

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If TLB entries are loaded on-demand, then TLB management simplicity is maintained, but translation lookup time increases

Engineering Contradiction:
ImproveTLB management simplicityVSAvoidtranslation lookup time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The system performs preliminary action by proactively loading TLB entries from the second level TLB into the first level TLB based on predicted access patterns. This prefetching mechanism reduces future translation lookup times while maintaining relatively simple TLB management through automated pattern recognition and loading

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If L1 cache lines are evicted to L2 cache, then cache capacity utilization is improved, but data access speed decreases

Engineering Contradiction:
Improvecache capacity utilizationVSAvoiddata access speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent applies preliminary action by prefetching TLB entries before they are needed, allowing the system to maintain better cache capacity utilization while preparing translation information in advance. This reduces the impact of evictions on data access speed by having translation entries ready before cache lines are evicted

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260079706A1Apparatus and Method for Prefetching from a Second Level Translation Lookaside Buffer (TLB) to a First Level TLB
Publication Date: 2026.03.19 INTEL CORP
  • US20260079706A1 patent drawing
  • US20260079706A1 patent drawing
  • US20260079706A1 patent drawing

AI summary

One embodiment of a method comprises: fetching a plurality of instructions from a memory; executing the plurality of instructions, wherein a subset of the plurality of instructions are to cause memory access operations; performing a lookup in a L1 TLB coupled to or integral to the out-of-order execution circuitry to attempt to locate first virtual to physical address translations; performing a lookup in a STLB coupled to or integral to the out-of-order execution circuitry in response to a miss at the L1 TLB; and prefetching, by prefetch circuitry, a first entry from the STLB into the L1 TLB, the prefetch circuitry to perform additional prefetches, wherein in a first operational mode, a plurality of sequential entries are to be prefetched from the STLB and, in a second operational mode, a plurality of entries indicated in a temporal pattern table entry corresponding to the first entry are to be prefetched.