L1D-L2 Cache Alias Detection via Tag Copying
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Solution Overview
Problem
Existing methods for addressing the cache alias problem in L1D caches, such as modifying cache size or using directory-based cache systems, face limitations in hardware architecture, cache subsystem type, and expandability, leading to performance and compatibility issues.
Innovation Solution
The proposed solution involves establishing a tag copy random access memory and a valid array to detect and manage alias issues between L1D and L2 caches, allowing for efficient detection and resolution of alias problems without restricting hardware architecture or increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the L1D cache is designed as VIPT type with virtual index physical tag to enable parallel access and improve performance, then access speed is improved, but cache alias problem occurs where multiple virtual addresses map to same physical address but are cached in different cache lines
Solution Approach 1:
The patent copies the tag content from L1D cache to L2 cache to create a tag copy. This copy is then used to detect alias problems by comparing the virtual addresses in L1D with the physical addresses in L2, enabling identification of cache alias issues without affecting the parallel access capability of the VIPT cache structure
Solution Approach 2:
The patent introduces L2 cache as an intermediary component to detect and resolve alias problems. The L2 cache stores tag copies and serves as a mediator to verify address mappings, allowing the L1D cache to maintain its high-speed VIPT operation while alias issues are detected through the intermediary L2 cache
2Reliability
If cache size or set association degree is modified to ensure virtual index bits are less than or equal to physical index bits, then alias problem is solved, but storage size of cache is greatly reduced, thus reducing processor chip performance
Solution Approach 1:
The patent adds a new dimension of detection by introducing L2 cache as a separate layer for storing tag copies. Instead of modifying L1D cache parameters, the solution operates in an additional dimensional space (L2 cache) to detect and resolve alias problems, thereby preserving L1D cache storage capacity while solving the alias issue
3Reliability
If page coloring technology is used in operating system to force alias bits of virtual addresses to remain same, then alias problem is solved, but design burden of operating system increases and compatibility of processor chip with operating system is reduced
Solution Approach 1:
The patent implements self-service by enabling the cache subsystem to automatically detect and resolve its own alias problems through the tag copy mechanism in L2 cache. This eliminates the need for operating system intervention or page coloring technologies, allowing the hardware to self-diagnose and self-correct alias issues without increasing OS design burden or reducing compatibility
4Reliability
If banks are added to VIPT cache and divided according to alias bits with simultaneous write to multiple banks, then alias problem is solved, but storage capacity of cache is reduced, bandwidth pressure of write request is increased, and power consumption of cache module is improved
Solution Approach 1:
The patent applies partial action by only copying necessary tag information to L2 cache rather than duplicating entire cache banks. This selective copying approach resolves alias detection needs while minimizing the additional hardware resources and power consumption compared to full bank duplication approaches
5Difficulty of detecting and measuring
If directory of downstream cache is used to record alias bit and detect alias problem, then alias detection is enabled, but cache sub-system must be designed as directory-based type which is not suitable for snoop-based cache sub-system
Solution Approach 1:
The patent achieves universality by designing the L2 cache tag copy mechanism that can function in both directory-based and snoop-based cache subsystems. The tag copying and comparison approach is architecture-agnostic, allowing the same mechanism to provide alias detection capability across different cache subsystem types without requiring directory-based design
Data Source
AI summary
The present disclosure is suitable for the field of hardware chip design, and particularly relates to an alias processing method and system based on L1D-L2 caches and a related device. A method for solving an alias problem of the L1D cache based on a L1D cache-L2 cache structure and a corresponding system module are disclosed. The method provided by the present disclosure can maximize hardware resource efficiency, without limiting a chip structure, a hardware system type, an operating system compatibility and a chip performance, and meanwhile, the module realized based on the cache cannot greatly increase power consumption of the whole system, thus having good expandability.