L1I Cache Controller Page Miss Translation Prefetch
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Solution Overview
Problem
The existing memory management systems face significant latency issues due to page miss translation, as they require tens to hundreds of cycles to fetch the next page translation entry from the MMU when a program fetch crosses a page boundary, leading to inefficiencies in memory access.
Innovation Solution
The proposed solution involves the L1I cache controller performing an a-priori lookup to determine if a virtual address crosses a page boundary and pipelining requests to the µTLB to prefetch the second page translation entry, storing it locally for immediate use when the boundary is crossed, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the next page translation entry is fetched from the MMU when a page boundary is crossed, then the address translation is accurate, but the translation latency increases significantly (tens to hundreds of cycles)
Solution Approach 1:
The patent applies preliminary action by prefetching the next page translation entry from the MMU before it is actually needed. When the current page translation is valid, the system proactively requests the next page's translation entry in advance, so that when a page boundary is crossed, the translation is already available in the µTLB, eliminating the latency penalty.
Solution Approach 2:
The patent introduces an intermediary mechanism (prefetch buffer) that stores pre-fetched translation entries. This buffer acts as a mediator between the MMU and the µTLB, holding advance-fetched translation data ready for immediate use when page boundaries are crossed, thus reducing the need for slow MMU access at critical moments.
2Reliability
If the system waits for the L1I cache controller to process page requests before prefetching, then the translation requests are processed in order, but the prefetching efficiency is reduced due to sequential processing
Solution Approach 1:
The patent segments the translation request processing by separating the prefetching function from the main request processing path. It creates dedicated prefetch logic that can independently initiate translation requests without waiting for the main L1I cache controller to finish processing current page requests, enabling parallel operation while maintaining correctness.
Solution Approach 2:
The patent implements dynamic request pipelining where multiple translation requests are issued in sequence without waiting for completion of previous requests. The system dynamically manages the pipeline of outstanding requests, allowing the L1I cache controller to begin processing subsequent page requests while previous requests are still being fulfilled, thus overlapping latency periods.
Data Source
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AI summary
Example embodiments hide the page miss translation latency for program fetches. In example embodiments, whenever an access is requested by a CPU, the L1l cache controller (111) does a-priori lookup of whether the virtual address plus the fetch packet count of expected program fetches crosses a page boundary (1614, 1622). If the access crosses a page boundary (1622), the L1l cache controller (111) will request a second page translation along with the first page. This pipelines requests to the μΤLΒ (1501) without waiting for L1l cache controller (111) to begin processing the second page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored (1624) locally in L1l cache controller (111) and used when the access crosses the page boundary.