L2 Cache Error Correction With Selective Hamming and Parity Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In digital data processors, soft errors caused by radiation can lead to corruption of data in cache memory, particularly in the level 2 cache, where data remains static for long durations, necessitating effective protection mechanisms to prevent unexpected behavior in the CPU.
Innovation Solution
A memory system with parity generation and storage that selectively forms and stores parity bits based on the state of a global enable bit, enabling detection and correction of errors in data sources, utilizing a Hamming code for efficient error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complete data correction is implemented in level 2 cache, then reliability against soft errors is improved, but area and memory bits required increase significantly
Solution Approach 1:
The patent applies different error protection mechanisms to different data types in the cache. Instructions receive distance-4 Hamming code protection (detect 2, correct 1) while data uses simpler parity bits. This local differentiation optimizes reliability where needed (instructions) while minimizing area overhead (data), directly resolving the contradiction between comprehensive error correction and cache area consumption.
Solution Approach 2:
The patent changes the error protection parameter from uniform complete correction to selective protection based on data type. By adjusting the Hamming code distance parameter (d=4 for instructions, d=2 for data), the system achieves adequate reliability with reduced overhead, resolving the area vs. reliability contradiction through parameter optimization.
2Reliability
If distance-4 Hamming code is used for all cache data, then error detection and correction capability is improved, but memory bit overhead increases
Solution Approach 1:
The patent implements local quality by applying distance-4 Hamming code only to instruction storage while using simpler parity protection for data. This selective approach provides enhanced error detection (detect 2) where it matters most for system reliability while minimizing the quantity of protection bits required, directly addressing the contradiction between detection capability and memory bit overhead.
3Reliability
If error protection is implemented in level 2 cache, then CPU reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error protection mechanism into distinct components: distance-4 Hamming code for instructions and parity bits for data. This segmentation allows independent optimization of each protection scheme, reducing overall device complexity while maintaining high CPU reliability through appropriate protection of critical instruction data.
Data Source
AI summary
This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.